TLK6002 Datasheet, PDF (80/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
www.ti.com
RATE_RX[1:0], write 4’b1101 to 1.3:0 PLL_MULT[3:0] to select EIGHTH rate and 20x MPY
(CHANNEL_CONTROL_1 = 0x01FD).
• Serial Configuration
– Configure the following bits per the desired application
• 1.9:8 (LOOP_BANDWIDTH[1:0])
• 2.12:8 (TWPOST1[4:0])
• 2.7:4 (TWPRE[3:0])
• 2.3:0 (SWING[3:0])
• 8.14:12 (EQPRE[2:0])
• 8.11:10 (CDRTHR[1:0]) = 2’b01
• 8.9:8 (CDRFMULT[1:0]) = 2’b00
• Mode Control
– Channel synchronization (comma enable) is on by default and the parallel output 9 bit codes are
byte aligned.
– Write 1’b1 to 3.3 ENCODE_ENABLE
– Write 1’b1 to 3.2 DECODE _ENABLE
– Set the DDR Source Aligned Mode
• Write 1’b1 to 3.6 DDR_ENABLE
• Write 1’b1 to 3.1 TX_EDGE_MODE to select Transmit DDR Source Aligned Mode
• Write 1’b1 to 3.0 RX_EDGE_MODE to select Receive DDR Source Aligned Mode
• If a different parallel IO align mode used:
– If SDR Falling Edge Aligned: write 0x018C to CHANNEL_CONTROL_3 register.
– If SDR Rising Edge Aligned: write 0x018F to CHANNEL_CONTROL_3 register.
– If DDR Source Centered: write 0x01CC to CHANNEL_CONTROL_3 register.
• Enable desired status signals to LOSA and LOSB for real time monitoring per channel. Any number of
signals can be enabled at once.
– If SERDES Rx Loss of Signal condition monitored: write 1’b1 to 6.10 LOS_OVERLAY.
– If channel synchronization status monitored: write 1’b1 to 6.9 CH_SYNC_OVERLAY.
– If PLL lock status monitored: write 1’b1 to 6.8 PLL_LOCK_OVERLAY.
– If invalid code word status monitored: write 1’b1 to 6.3 INVALID_CODE_OVERLAY
– If SERDES AGC unlock status monitored: write 1’b1 to 7.7 AGCLOCK_OVERLAY.
– If SERDES AZDONE status monitored: write 1’b1 to 7.6 AZDONE_OVERLAY.
• Check SERDES PLL Status for Locked State
– Poll 5.0 PLL_LOCK (per channel) until it is asserted (high).
• Toggle ENRX
– Write 1’b0 to 20.2 (ENRX)
– Write 1’b1 to 20.2 (ENRX)
• Final CDR Configuration
– Wait until either AGC_LOCKED asserted or 250M UI
– Write 8.9:8 (CDRFMULT[1:0]) = 2’b01
– Poll 5.13 AGC_LOCKED (1’b1) (per channel)
• Issue Data path Reset
– Write 1’b1 to 4.3 DATAPATH_RESET
• Clear Latched Registers
– Read 5 CHANNEL_STATUS_1 to clear all (per channel)
– Read 14.15:0 ERROR_COUNTER to clear (per channel)
• Device provisioning has completed at this point
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ELECTRICAL SPECIFICATIONS
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