TLK6002 Datasheet, PDF (22/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
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2.7 16-bit DDR (Double Data Rate) Mode (8b/10b Encoder/Decoder Enabled)
When DDR is enabled with the 8b/10b encoder enabled, the data format is identical to that of "16-bit SDR
(Single Data Rate) Mode (8b/10b Encoder/Decoder Enabled)" mode, except that four symbols are
transferred per parallel interface clock cycle instead of two. See the referenced previous section for further
details.
2.8 Parallel Interface Clocking Modes
The TLK6002 supports source centered timing and source aligned DDR timing on the parallel receive
output bus. TLK6002 also supports rising edge aligned and falling edge aligned SDR timing on the parallel
receive output bus. See Figure 2-4 for more details.
RXCLK_A
Source Centered (DDR)
RDA_ [19:0 ]
t_SETUP t_HOLD t_SETUP t_HOLD
Data
Data
Source Aligned (DDR)
RDA_ [19:0]
Data
Data
Falling Edge Aligned (Rising Edge Sampled) (SDR)
RDA_ [19:0]
Data
Data
Rising Edge Aligned (Falling Edge Sampled ) (SDR)
RDA_ [19:0]
Data
Data
Data
Figure 2-4. Receive Interface Timing – Source Centered/Aligned (Channel A is shown).
The transmit input timing modes are shown in Figure 2-5.
Transmit SDR/DDR input timing modes supported are similar to RX modes.
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Description
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