TLK6002 Datasheet, PDF (71/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

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TLK6002
SLLSE34 – MAY 2010
RXCLK_x
Tpd
Tpd
V_OH(ac)
RDx
VDDQ/2
V_OL(ac)
V_OH(ac)
VDDQ/2
V_OL(ac)
Figure 4-13. HSTL (DDR Timing Mode Only) Source Aligned Output Timing Requirements
4.11
T_duty
t_period
T_freq
T_pd
HSTL Output Switching Characteristics (SDR Timing Mode Only)
PARAMETER
RXCLK_x⁽¹⁾ Duty Cycle
RXCLK_x Period
RXCLK_x Frequency
RXCLK_x rising to RDx⁽³⁾ valid.
CONDITION
Rising and Falling Edge Aligned Data⁽²⁾
Rising and Falling Edge Aligned Data
Rising and Falling Edge Aligned Data
Rising Edge Aligned, See Figure 4-14.⁽²⁾
RXCLK_x falling to RDx valid.
Falling Edge Aligned, See Figure 4-15.⁽²⁾
(1) RXCLK_x refers to RXCLK_A or RXCLK_B for channels A and B respectively.
(2) Cload = 10pF, using timing reference of (VDDQA/B)/2.
(3) RDx refers to either RDA or RDB for channels A and B respectively.
MIN
40%
3.2
23.5
–0.10 ×
t_period
–0.10 ×
t_period
MAX
60%
42.55
312.5
+0.10 ×
t_period
+0.10 ×
t_period
UNIT
ns
MHz
ps
ps
RXCLK_x
t_PERIOD
V_OH(ac)
VDDQ/2
V_OL(ac)
V_OH(ac)
RDx ^VDDQ/2
V_OL(ac)
T_PD
Figure 4-14. HSTL (SDR Timing Mode Only) Rising Edge Aligned Output Timing Requirements
RXCLK_x
t_PERIOD
V_OH(ac)
RDx ^VDDQ/2
V_OL(ac)
T_PD
V_OH(ac)
VDDQ/2
V_OL(ac)
Figure 4-15. HSTL (SDR Timing Mode Only) Falling Edge Aligned Output Timing Requirements
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