TLK6002 Datasheet, PDF (23/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

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TLK6002
SLLSE34 – MAY 2010
TXCLK _A
Source Centered (DDR)
TDA_ [19:0]
t_SETUP
t_HOLD t_SETUP
t_HOLD
Data
Data
Source Aligned (DDR)
TDA_ [19:0]
Data
Data
Falling Edge Aligned (Rising Edge Sampled ) (SDR)
TDA_[19:0]
Data
Data
Rising Edge Aligned (Falling Edge Sampled ) (SDR)
TDA_ [19:0]
Data
Data
Data
Figure 2-5. Transmit Interface Timing (Channel A is shown).
2.9 Scrambler and De-scrambler
TLK6002 incorporates a scrambling function located before the 8b/10b encoder in the transmit datapath,
and a de-scrambling function located after the 8b/10b decoder in the receive datapath. The scrambler and
de-scrambler can be enabled/disabled using the MDIO management serial interface.
The transmitter applies a 7-degree polynomial to data bytes (not control), and the inverse operation is
performed by the receiver.
The scrambler/descrambler should be disabled if the 8b/10b encoder/decoder is disabled.
To achieve randomness between transmitting lanes, transmitters can be programmed to have differing
scrambling offset. Each transmitter seed value is programmed into a register which will be used by that
transmitter. The user should program unique seed values for adjacent TX links.
The receivers also have their own de-scrambling seed value registers. The receiver’s de-scrambling seed
value must be programmed to be the same as the corresponding transmitting end of the link. There is no
training sequence for transmitting the seed values to the receiver.
The scrambler is a 7-degree polynomial, linear feedback shift register (LFSR). The polynomial is; (X⁷ + X⁶
+ 1). K28.1, K28.5, or K28.7 characters reset the LFSR to the seed value. The bit pattern repeats every
127 bits.
Copyright © 2010, Texas Instruments Incorporated
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