TLK6002 Datasheet, PDF (6/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
RXCLK_A
S/W
{3.9,3.8}
00 TXBCLK_A
DDR: 4 ^{01 RXBCLK_A}
SDR: 2 ^{10 TXBCLK_B}
11 RXBCLK_B
RDA_[19:0]
RDB_[19:0]
0
1
S/W
3.9
S/W
3.9
0
1
RX A FIFO
RX B FIFO
RXCLK_B
S/W
{3.9,3.8}
00 TXBCLK_B
DDR: 4 01 RXBCLK_B
SDR: 2 10 TXBCLK_A
11 RXBCLK_A
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RXDA_INT[9:0]
RXBCLK_A
CH A RX
TXDAaDtaaptaatphath
RXDB_INT[9:0]
CH B RX
RXBCLK_B
TXDAaDtaaptaatphath
RXDA[9:0]
RXBCLK_A
RXDB[9:0]
RXBCLK_B
Channel A
TRXXASDEaRtaDpEaSth
Channel B
TRXXASDEaRtaDpEaSth
Legend:
= Primary Device Pin
S/W
x.x:x
= Software Programmable / Register Address.Bit
RXBCLK_*, TXBCLK_* frequency is Serial Bit Rate Divided by 10
Line rates for CPRI
614.4 /
1228. 8 /
2457. 6 /
3072 /
4915. 2 /
6144 Mbps
CPRI /
OBSAI
TLK6002
TLK3131 /
32 /34
Serdes
Figure 1-5. TLK6002 Receive Clock Architecture
Line rates for OBSAI
768 /
1536 /
3072 /
6144Mbps
ADS5232
ADS5240
ADS528 x
I/Q
FPGA
DDC
12- bit
ADC
GC 6016
ADC
DR
LNA
TX _CLK
61. 44 MHz
IF 2
IF 1
61. 44 MHz
CDCEX52005
TLK 6002
( Serdes
RX_CLK
X - tal
I/Q
FPGA
DUC
GC 6016
61.44 MHz
245.76 MHz
FIR
16 - bit
DAC
16 - bit
FIR
DAC
LO _ 1
0
90
Σ
DAC5682 z
DAC 5688
DAC 5687
LO _ 1
Figure 1-6. TLK6002 Application Diagram
RF
Duplexer
PA
6
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