TLK6002 Datasheet, PDF (38/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
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2.22 Transmit Serial Output During ARS Mode
The transmit serial output is always actively driven during ARS mode. The user has flexibility in the value
transmitted by the serial output during ARS. Note that since the PLL is shared between a TX and RX
channel, that the transmit serial rate will automatically follow the rate setting which ARS is validating in the
receive direction (whether it is subsequently determined to be correct or not).
The following bits impact transmitted serial output data:
1. ARS_TX_DATAPATH_OVERRIDE – ARS Transmit Datapath Override – (per channel Register bit
10.10) – When asserted, in tandem with register (ARS_TX_DATA[9:0], register bits 10.9:0), any fixed
or repeating sequence of 10 bits can be transmitted during ARS. When deasserted, the transmit
parallel interface input data is transmitted and serialized as received during ARS (and may not be
deterministic as the TX FIFO will collide on each rate change unless a fixed (static) pattern is input into
the parallel input interface making the fifo collision unimpacting to the datapath).
2. ARS_TX_MDIO_GATE – ARS Transmit MDIO Gate – per channel Register bit 10.11 – This bit is only
relevant if TX_DATAPATH_OVERRIDE is asserted. When this bit is deasserted, upon successful ARS
rate determination, the transmit datapath TX FIFO is automatically reset (centered) and continuity
between the parallel input data and serial output is established without MDIO interaction. When this bit
is asserted, the transmit datapath will not automatically switch over to serializing parallel input data at
the time the ARS state machine successfully validates the incoming serial data rate (although the TX
and RX FIFO are both automatically reset). This will give the opportunity for local MDIO firmware to
interactively manage any additional device settings. Specifically this gives the device interfacing to
TLK6002 the opportunity to read MDIO registers to determine the validated incoming serial rate,
manage any other device or system settings required, and also manage TXCLK_A/B synchronicity to
REFCLK at the proper data rate. After these steps are complete, the final step is to recenter the TX
FIFO (by manually issuing a TX FIFO reset (TXFIFO_RESET register bit 4.2). Transmit datapath
reliable operation is fully restored after the TX FIFO reset MDIO write transaction is completed, and
datapath continuity between parallel inputs and serial outputs is established.
At the time when ARS rate determination is successful, both a TX and RX FIFO reset is automatically
issued internal to TLK6002. Please note that if ARS_TX_MDIO_GATE is not asserted, there may be
difficulty in effectively recentering the transmit fifo. Anytime the TX FIFO collides, it automatically recenters
itself. This automatic recentering is triggered by the TXCLK_A/B and SERDES TX byte clock (multiplied
up and divided down REFCLK_A/B) being asynchronous or having excessive phase drift. The TX FIFO is
only effectively centered when the relationship between these two clocks has stabilized, at which point
issuing a TX FIFO reset (manual or automatic through collision) will optimally center the TX FIFO. Note
that careful external control of the TXCLK_A/B and REFCLK relationship (0 ppm and TXCLK_A/B at the
right data rate) must be managed for the mode where ARS_TX_MDIO_GATE is deasserted to work
reliably. If the clock relationship is still changing at the time of automatic recenter, the fifo may at some
point in the future need to automatically recenter itself (via collision), at which time the transmit serial data
will be briefly corrupted before resuming reliable operation. It is recommended that ARS_TX_MDIO_GATE
is asserted unless careful system operation has been analyzed.
In any ARS mode, note that the receive datapath software reset (not the same as RX FIFO reset) should
not be issued as channel synchronization will be lost, and ARS would inappropriately begin searching for
the incoming serial rate again (which is undesirable).
2.22.1 Receive Parallel Output Data During ARS Mode
The parallel outputs are always driven during ARS mode. During ARS mode, it is anticipated that channel
synchronization will typically remain lost during the rate determination process, and thus the parallel output
data will typically behave predictably as indicated in the previous paragraph labeled Receive Datapath
Error Condition Operation.
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