TLK6002 Datasheet, PDF (54/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
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Table 3-15. ARS_CONTROL_1
BIT(s)
10.15
Address: 0x0A
NAME
ARS_RX_CLK_EN
10.14 ARS_ LOCK_OVERLAY
10.13:12 ARS_ EN[1:0]
10.11 ARS_TX_MDIO_GATE
10.10 ARS_TX_DATAPATH_OVERRIDE
10.9:0 ARS_TX_DATA[9:0]
Default: 0x0800
DESCRIPTION
ACCESS
Valid only when ARS function is enabled.
RW
0 = Holds parallel output clock RXCLK_x output fixed at zero until serial data
rate is determined by the ARS. (Default 1’b0)
1 = Allows RXCLK_x output to toggle normally.
Valid only when ARS function is enabled.
RW
0 = LOSx pin does not reflect ARS loss of lock status (Default 1’b0)
1 = Allows ARS loss of lock status to be reflected on LOSx pin
ARS enable software control. Applicable when RATE_x[2:0] pins are set to
RW
3’b100.
00 = Serdes settings are determined by MDIO (Default 2’b00)
01 = Enable ARS function in respective channel.
Serdes settings for respective channel are determined by ARS in the same
channel. Refer RATE_x[2:0] 3’b101 setting for more information.
10 = Enable ARS function in respective channel.
Serdes settings for respective channel are determined by ARS in the same
channel. Refer RATE_x[2:0] 3’b110 setting for more information.
11 = Enable ARS function in respective channel as slave mode.
If ARS is enabled in partner channel, serdes settings in this channel are
determined by ARS in partner channel.
If ARS is not enabled in partner channel, serdes settings in this channel are
determined by MDIO.
Refer RATE_x[2:0] 3’b111 setting for more information.
Valid only when ARS_TX_DATAPATH_OVERRIDE (10.10) is set
RW
0 = When ARS successfully determines incoming serial data rate, TX_FIFO
is automatically reset and parallel data is serialized and sent through serial
output pins.
1 = When ARS successfully determines incoming serial data rate, TX FIFO
needs to be manually reset by writing to register bit 4.2 to enable proper
serialization of the parallel data. (Default 1’b1)
Applicable during serial data rate determination by ARS
RW
0 = Transmit parallel input data is serialized as received and sent through
serial output pins. (Default 1’b0)
1 = 10 bit data specified in ARS_TX_DATA (10.9:0) is serialized and sent
through serial output pins.
10 bit data to be serialized during serial rate determination by ARS.
RW
If TX_PMA_BIT_ORDER (8.3) is set, ARS_TX_DATA [9] is serially
transmitted first else ARS_TX_DATA [0] is serially transmitted first.
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