TLK6002 Datasheet, PDF (40/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
2.23 Output Clock Selection (CLK_OUT_P/N)
Table 2-9 details CLK_OUT_P/N as a function of device settings.
Table 2-9. CLK_OUT_P/N Frequencies (ARS Enabled and Disabled)
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RATE_A[2:0]
000/001/010/011
000/001/010/011
110
110
110
110
Not 110
Not 110
Not 110
Not 110
101
101
101
101
101
000/001/010/011
000/001/010/011
000/001/010/011
000/001/010/011
000/001/010/011
101
101
101
101
101
101
101
101
111
111
111
111
111
111
101/110
101/110
101/110
101/110
000/001/010/011/111
000/001/010/011/111
RATE_B[2:0]
000/001/010/011
000/001/010/011
Not 110
Not 110
Not 110
Not 110
110
110
110
110
000/001/010/011
000/001/010/011
000/001/010/011
000/001/010/011
000/001/010/011
101
101
101
101
101
101
101
101
101
101
101
101
101
101/110
101/110
101/110
101/110
000/001/010/011/111
000/001/010/011/111
111
111
111
111
111
111
CLK_OUT_SEL
0
1
x
x
x
x
x
x
x
x
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
x
x
x
x
0
1
x
x
x
x
0
1
CLK_OUT_P/N
RXBCLK_A/(0.5:4)
RXBCLK_B/(0.5:4)
153.6 MHz (ppm 0 to RXAP/N)
61.44 MHz (ppm 0 to RXAP/N)
153.6 MHz (ppm 0 to RXAP/N)
61.44 MHz (ppm 0 to RXAP/N)
153.6 MHz (ppm 0 to RXBP/N)
61.44 MHz (ppm 0 to RXBP/N)
153.6 MHz (ppm 0 to RXBP/N)
61.44 MHz (ppm 0 to RXBP/N)
153.6 MHz (ppm 0 to RXAP/N)
61.44 MHz (ppm 0 to RXAP/N)
153.6 MHz (ppm 0 to RXAP/N)
61.44 MHz (ppm 0 to RXAP/N)
RXBCLK_B/(0.5:4)
153.6 MHz (ppm 0 to RXBP/N)
61.44 MHz (ppm 0 to RXBP/N)
153.6 MHz (ppm 0 to RXBP/N)
61.44 MHz (ppm 0 to RXBP/N)
RXBCLK_A/(0.5:4)
153.6 MHz (ppm 0 to RXAP/N)
61.44 MHz (ppm 0 to RXAP/N)
153.6 MHz (ppm 0 to RXAP/N)
61.44 MHz (ppm 0 to RXAP/N)
153.6 MHz (ppm 0 to RXBP/N)
61.44 MHz (ppm 0 to RXBP/N)
153.6 MHz (ppm 0 to RXBP/N)
61.44 MHz (ppm 0 to RXBP/N)
153.6 MHz (ppm 0 to RXBP/N)
61.44 MHz (ppm 0 to RXBP/N)
153.6 MHz (ppm 0 to RXBP/N)
61.44 MHz (ppm 0 to RXBP/N)
RXBCLK_A/(0.5:4)
RXBCLK_B/(0.5:4)
153.6 MHz (ppm 0 to RXAP/N)
61.44 MHz (ppm 0 to RXAP/N)
153.6 MHz (ppm 0 to RXAP/N)
61.44 MHz (ppm 0 to RXAP/N)
RXBCLK_A/(0.5:4)
RXBCLK_B/(0.5:4)
Selected Channel A
Selected Channel B
REFCLK Frequency (MHz)
REFCLK Frequency (MHz)
Indicated By ARS_REF_FREQ Indicated By ARS_REF_FREQ
x
x
x
x
153.6
x
122.88
x
307.2
x
245.76
x
x
153.6
x
122.88
x
307.2
x
245.76
153.6
x
122.88
x
307.2
x
245.76
x
x
x
x
153.6
x
122.88
x
307.2
x
245.76
x
x
153.6
x
122.88
x
307.2
x
245.76
x
x
153.6
x
122.88
x
307.2
x
245.76
x
153.6
x
122.88
x
307.2
x
245.76
x
x
x
x
153.6
x
122.88
x
307.2
x
245.76
x
x
x
x
x
2.24 MDIO Management Interface
The TLK6002 supports the Management Data Input/Output (MDIO) Interface as defined in Clause 22 of
the IEEE 802.3 Ethernet specification. The MDIO allows register-based management and control of the
serial links. Normal operation of the TLK6002 is possible without use of this interface. However, some
features are accessible only through the MDIO.
The MDIO Management Interface consists of a bi-directional data path (MDIO) and a clock reference
(MDC). The port address is determined by control pins (see Table 2-10).
40
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