TLK6002 Datasheet, PDF (11/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
www.ti.com
SLLSE34 – MAY 2010
Table 2-1. Pin Description – Signal Pins (continued)
Terminal
Signal
BGA
Direction
Type
Supply
Description
LOSB
Channel B Receive Loss Of Signal (LOS) Indicator.
LOSB=0, signal detected.
LOSB=1, Loss of signal (6.10 enabled).
Loss of signal detection is based on the input signal level.
Output
LVCMOS
When RXBP/N has an input signal of ≤75 mVdfpp, LOSB will be asserted (if enabled). The input signal should be ≥
150 mVdfpp for this function to operate reliably.
V17
1.5V/1.8V _{Other functions can be observed on LOSB realtime, configured via MDIO.}
VDDO2 40Ω
Driver
During device reset (RESET_N asserted low) this pin is driven low.
During pin based power down (PD_TRXB_N asserted low), this pin is floating.
During register based power down (1.15 asserted high), this pin is floating.
It is highly recommended that LOSB be brought to easily accessible point on the application board (header), in the
event that debug is required.
PD_TRXB_N
Input
Transceiver Power down. When this pin is held low (asserted), Channel B is placed in power down mode. When
U15
LVCMOS
1.5V/1.8V
deasserted , Channel B operates normally. After deassertion, a software datapath reset should be issued through
the MDIO interface.
VDDO2
Signals common to Channels A and B:
REFCLK_0_P/N
B5
A5
Input LVDS/
LVPECL
DVDD
Reference Clock Input Zero. This differential input is a clock signal used as a reference to either or both of the
bidirectional SERDES macros. It can be routed internally to either SERDES macro using device pins
(REFCLK_A_SEL and REFCLK_B_SEL) or through software registers. This input signal must be AC coupled. See
Figure 1-3. TLK6002 Reference Clock / Output Clock Architecture for more detail. If unused, REFCLK_0_P/N
should be pulled down to DGND through a shared 100Ω resistor.
REFCLK_1_P/N
C6
D6
Input LVDS/
LVPECL
DVDD
Reference Clock Input One. This differential input is a clock signal used as a reference to either or both of the
bidirectional SERDES macros. It can be routed internally to either SERDES macro using device pins
(REFCLK_A_SEL and REFCLK_B_SEL) or through software registers. This input signal must be AC coupled. See
Figure 1-3. TLK6002 Reference Clock / Output Clock Architecture for more detail. If unused, REFCLK_1_P/N
should be pulled down to DGND through a shared 100Ω resistor
REFCLK_A_SEL R6
Input
LVCMOS
1.5V/1.8V
VDDO3
Reference Clock Select Channel A. This input, when low, selects REFCLK_0_P/N as the clock reference to
Channel A SERDES macro. When high, REFCLK_1_P/N is selected as the clock reference to Channel A SERDES
macro. If software control is desired (register bit 0.1), this input signal should be tied low. See Figure 1-3. TLK6002
Reference Clock / Output Clock Architecture for more detail.
REFCLK_B_SEL T2
Input
LVCMOS
1.5V/1.8V
VDDO3
Reference Clock Select Channel B. This input, when low, selects REFCLK_0_P/N as the clock reference to
Channel B SERDES macro. When high, REFCLK_1_P/N is selected as the clock reference to Channel B SERDES
macro. If software control is desired (register bit 0.0), this input signal should be tied low. See Figure 1-3. TLK6002
Reference Clock/Output Clock Architecture for more detail.
PRBS_EN
Enable PRBS: When this pin is asserted high, the internal PRBS generator and verifier circuits are enabled on both
transmit and receive data paths of both channels.
This signal is logically OR’d with an mdio register bit.
R16
Input
LVCMOS
1.5V/1.8V
PRBS 2³¹-1 is selected by default, and can be changed in MDIO register 7.10:8.
Note that PRBS is not possible in eighth rate mode.
VDDO2
The PRBS_EN pin should be routed to an uninstalled header so that it could be driven externally in the event that
device debug is required. In application mode, it should be biased with a pull up or pull down resistor (or allow for
an isolation mechanism from the on board driver), and not connected directly to a power or ground plane.
CLK_OUT_P/N
J6
J7
Output CML
DVDD
Recovered Byte Clock. If ARS is not enabled, and CLK_OUT_SEL is low, an optionally divided version of Channel
A recovered byte clock is output onto CLK_OUT_P/N. If ARS is not enabled, and CLK_OUT_SEL is high, an
optionally divided version of Channel B recovered byte clock is output onto CLK_OUT_P/N. The recovered byte
clock is synchronous to the incoming serial data rate for the selected channel. See Figure 1-3. TLK6002 Reference
Clock/Output Clock Architecture for more detail. The recovered byte clock can be divided by one, two, four, or eight
as selected in an mdio register.
If ARS is enabled, the CLK_OUT_P/N output is selected via Table 2-9.
This CML output must be AC coupled.
During device reset (RESET_N asserted low) this pin is driven differential zero. During pin based power down
(PD_TRXA_N and PD_TRXB_N asserted low), these pins are floating.
During register based power down (1.15 asserted high both channels), these pins are floating.
CLK_OUT_SEL T15
Input
LVCMOS
1.5V/1.8V
VDDO2
Output Clock Selection. If ARS is not enabled and CLK_OUT_SEL is low, Channel A recovered byte clock is
output onto CLK_OUT_P/N. If ARS is not enabled and CLK_OUT_SEL is high, Channel B recovered byte clock is
output onto CLK_OUT_P/N. If software control is desired (register bit 0.6), this input signal should be tied low. See
Figure 1-3. TLK6002 Reference Clock / Output Clock Architecture for more detail. If ARS is enabled, the function of
CLK_OUT_SEL is shown in Table 2-9.
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