TLK6002 Datasheet, PDF (25/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
www.ti.com
SLLSE34 – MAY 2010
Current Mode Logic (CML) drivers often require external components. The disadvantage of the external
component is a limited edge rate due to package and line parasitic. The CML driver on TLK6002 has
on-chip 50Ω termination resistors terminated to VDDT, providing optimum performance for increased
speed requirements. The transmitter output driver is highly configurable allowing output amplitude and
de-emphasis to be tuned to a channel's individual requirements. Software programmability allows for very
flexible output amplitude control. Only AC coupled output mode is supported.
When transmitting data across long lengths of PCB trace or cable, the high frequency content of the signal
is attenuated due to the skin effect of the media. This causes a "smearing" of the data eye when viewed
on an oscilloscope. The net result is reduced timing margins for the receiver and clock recovery circuits. In
order to provide equalization for the high frequency loss, 3-tap finite impulse response (FIR) transmit
de-emphasis is implemented. A highly configurable output driver maximizes flexibility in the end system by
allowing de-emphasis and output amplitude to be tuned to a channel’s individual requirements. Output
swing control is via MDIO.
See Figure 4-2 for output waveform flexibility. The level of de-emphasis is programmable via the MDIO
interface through control registers (2.12:4) through pre-cursor and post-cursor settings. Users can control
the strength of the de-emphasis to optimize for a specific system requirement.
2.14 High Speed Receiver
The high speed receiver is differential CML with internal termination resistors. The receiver requires AC
coupling. The termination impedances of the receivers are configured as 100Ω with the center tap weakly
tied to 0.8×VDDT with a capacitor to create an AC ground.
TLK6002 receiver incorporates an adaptive equalizer. This circuit compensates for channel insertion loss
by amplifying the high frequency components of the signal, reducing inter-symbol interference.
Equalization can be enabled or disabled per register settings. Both the gain and bandwidth of the
equalizer are controlled by the receiver equalization logic.
2.15 Loss Of Signal Output Signal Generation (LOS)
Loss of input signal detection is based on the voltage level of each serial input signal RXAP/N and
RXBP/N. Anytime the serial receive input differential signal peak to peak voltage level is ≤75 mVdfpp,
LOSA or LOSB are asserted (high true) respectively for Channel A and Channel B (if enabled, disabled by
default). Note that an input signal ≥ 150 mVdfpp is required for reliable operation of the loss of signal
detection circuit. If the input signal is between these two ranges, the SERDES will operate properly, but
the LOS indication will not be valid (or robust). The LOS indications are also directly readable through the
MDIO interface in register bits (5.2). The LOS indication per channel can be enabled through register bit
6.10 (defaults to disabled).
The following additional critical status conditions can be combined with the loss of signal condition
enabling additional realtime status signal visibility on the LOSA and LOSB outputs per channel:
1. GPI1 – Inverted and Logically OR'd (Register 6.11 enable) with LOS condition(s) when enabled – This
input signal, when enabled (disabled by default), is inverted and logically OR'd with the internally
generated LOS condition (on both channels) to allow easy overlay of additional board or external
device status with the other LOSA/LOSB indications.
2. Loss of Channel Synchronization Status – Logically OR'd with LOS condition(s) when enabled –
(Register 6.9 enabled). Loss of channel synchronization can be optionally logically OR'd (disabled by
default) with the internally generated LOS condition (per channel). In 20-bit operational mode, the
comma detection circuit must be enabled to actually enable this OR function. If it is not, this function is
not OR'd with the other LOS generating conditions. This bit should not be enabled unless comma
detection is enabled.
3. Loss of PLL Lock Status – Logically OR'd with LOS condition(s) when enabled – (Register 6.8
enabled). The internal PLL loss of lock status bit is optionally OR'd (disabled by default) with the other
internally generated loss of signal conditions (per channel).
Copyright © 2010, Texas Instruments Incorporated
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