TLK6002 Datasheet, PDF (83/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
www.ti.com
SLLSE34 – MAY 2010
4.19.2 PRBS TEST GENERATION AND VERIFICATION PROCEDURES
Use one of the following procedures to generate and verify the respective PRBS test patterns. It is
assumed that an appropriate external cable has been connected between serial outputs and serial inputs.
No external parallel side connections are necessary.
4.19.2.1 2⁷-1 / 2²³-1 / 2³¹-1 PRBS Register Based Testing
• Note: PRBS TX does not support eighth rate mode.
• Reset Device:
– Issue a hard or soft reset (RESET_N asserted -or- Write 1 to 0.15 GLOBAL_RESET)
• Select SERDES Reference Clock Input:
– If REFCLK_0_P/N used – Ensure REFCLK_A_SEL (or REFCLK_B_SEL if channel B is used)
primary input pin is low
– If REFCLK_1_P/N used – Ensure REFCLK_A_SEL (or REFCLK_B_SEL if channel B is used)
primary input pin is high
• Ensure a legal reference clock operation frequency is selected based on Appendix B (Continuous Rate
Device Configuration), and provision CHANNEL_CONTROL_1 register accordingly. (Note: Eighth
Rate TX Is Not Supported).
• Serial Configuration
– Configure the following bits per the desired application:
• 1.9:8 (LOOP_BANDWIDTH[1:0])
• 2.12:8 (TWPOST1[4:0])
• 2.7:4 (TWPRE[3:0])
• 2.3:0 (SWING[3:0])
• 8.14:12 (EQPRE[2:0])
• 8.11:10 (CDRTHR[1:0]) = 2’b01
• 8.9:8 (CDRFMULT[1:0]) = 2’b00
• 1.3:0 PLL_MULT[3:0]
• 1.7:6 RATE_TX[1:0]
• 1.5:4 RATE_RX[1:0]
• Check SERDES PLL Status for Locked State
– Poll 5.0 PLL_LOCK (per channel) until it is asserted (high).
• Toggle ENRX
– Write 1’b0 to 20.2 (ENRX)
– Write 1’b1 to 20.2 (ENRX)
• Select Test Pattern:
– If 2⁷-1 PRBS Pattern is desired:
• Write 3’b101 to 7.10:8 TEST_PATTERN_SEL[2:0]
– If 2²³-1 PRBS Pattern is desired:
• Write 3’b110 to 7.10:8 TEST_PATTERN_SEL[2:0]
– If 2³¹-1 PRBS Pattern is desired:
• Write 3’b111 to 7.10:8 TEST_PATTERN_SEL[2:0]
• Enable Test Pattern Generation:
– Write 1’b1 to 7.13 TP_GEN_EN
• Final CDR Configuration
– Wait until either AGC_LOCKED asserted or 250M UI
– Write 8.9:8 (CDRFMULT[1:0]) = 2’b01
– Poll 5.13 AGC_LOCKED (1’b1) (per channel)
• Issue Data path Reset
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