TLK6002 Datasheet, PDF (37/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

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TLK6002
SLLSE34 – MAY 2010
ARS Enabled
En? No
Yes
Start
Timeout
Counter
Change SERDES Settings
Disable ENRX
Drive ENPLL Low
>16?
No
Check Highest
Enabled Serial
Bit Rate
PLL
Lock?
Yes
No
Wait for PLL Lock
TO?
Yes
No
PLL
Lock?
Yes
Enable ENRX &
Wait For AZDONE
>16 &
AZDONE No
Ye?s
Automatic Datapath Reset
Set
ARS_PLL_LOCK_ERR
Bit
Check CH Synchronization
Yes TO?
Check Next Lower
Enabled Serial Bit Rate
(If at lowest rate , go to
highest enabled rate )
Sync?
Yes
No
TX FIFO and
RX FIFO
Auto Reset
No
MDIO
Gate
Yes
Try Last
Successful (Same)
Serial Bit Rate
One More Time Before
Continuing With Next
Lower Enabled Rate
Wait for TX FIFO RST
(ARS Locked)
ARS Locked
Yes Sync?
No
MDIO
Yes FIFO RST No
?
Legend:
TO = X*1024 REFCLK Period Counter Timeout
Sync = Channel Synchronization & (AGCLOCK |
!AGCLOCK_EN) & (!6.6 | !LOS)
>16 = Greater Than or Equal to 16 REFCLK Periods
Mdio Gate = ARS_MDIO_GATE
MDIO FIFO RST = Mdio Write to Set TX FIFO RST
Figure 2-13. ARS State Machine Flowchart
Copyright © 2010, Texas Instruments Incorporated
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Description
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