TLK6002 Datasheet, PDF (91/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
www.ti.com
SLLSE34 – MAY 2010
Table 8-2. Device Absolute Receive Latency – SDR and DDR Modes
RX SDR/DDR RECEIVE ABSOLUTE LATENCY
Note: RX FIFO Depth (When FIFO Enabled) is 4 words.
Latency Components
Item
Minimum Maximum
Description
A
47
57
Serial Input Bit to RX SERDES Output Register
B
10
10
RX SERDES Output Register to RX PMA Register
C
10
10
RX PMA Register to Channel Sync Input Register
D
10
20
Channel Sync Input Register to Channel Sync Output Register
E
10
10
Channel Sync Output Register to 8b/10b Decoder Input Register
F
10
10
8b/10b Decoder Input Register to 8b/10b Output Register
G
10
10
8b/10b Output Register to RX FIFO Input Register
H
10
40
RX FIFO Input Register to RX FIFO Output Register
I
10
20
RXFIFO Output Register to RX Parallel Output Register Driven
Bit Detail
RX*_[19]
RX*_[10]
RX*_[9]
RX*_[0]
Latency
0
9
0
9
Minimum
127
136
127
136
Maximum
187
196
187
196
Assumption: RX*_[10 and 0] are the first received bits.
Disabling Channel Synchronization Reduces Above Numbers by 20 Minimum and 30 Maximum bit times.
Disabling Decoder Reduces Above Numbers by 20 bit times.
Bypassing RX FIFO Reduces Above Numbers by 20 Minimum and 50 Maximum bit times.
Latency
Summary
RX*_[19]
RX*_[10]
RX*_[9]
RX*_[0]
RX FIFO
Bypassed
Channel
Sync On
8b/10b
Decoder On
Minimum
107
116
107
116
Maximum
137
146
137
146
RX FIFO
Bypassed
Channel Sync
On
8b/10b Decoder
Off
Minimum
87
96
87
96
Maximum
117
126
117
126
RX FIFO
Bypassed
Channel
Sync Off
8b/10b
Decoder Off
Minimum
67
76
67
76
Maximum
87
96
87
96
RX FIFO
Enabled
Channel
Sync On
8b/10b
Decoder On
Minimum
127
136
127
136
Maximum
187
196
187
196
Table 8-3 show the static latency variance. Note that static latency variation is the difference in absolute
latency values possible across device reset/power ups.
Copyright © 2010, Texas Instruments Incorporated
Appendix D – Device Latency Specification
91
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