TLK6002 Datasheet, PDF (12/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
www.ti.com
Terminal
Signal
BGA
V15
M8
PRTAD[4:0]
K12
K11
L11
RESET_N
V1
MDC
T1
MDIO
U2
SCL
H13
SDO
K13
SDI
E14
CS_N
D14
Table 2-1. Pin Description – Signal Pins (continued)
Direction
Type
Supply
Description
Port Address. Used to select the Port ID.
PRTAD[4:1] selects the device port address. TLK6002 has two different PHY addresses (ports). Selecting a unique
PRTAD[4:1] per TLK6002 device allows 16 TLK6002 devices per MDIO bus. Each channel can be accessed by
setting the appropriate port address field within the serial interface protocol transaction.
Input
LVCMOS
1.5V/1.8V
VDDO2/
VDDO1/
VDDO1/
VDDO1/
VDDO1
TLK6002 will respond if the 4 MSB’s of the inband PHY address field on MDIO protocol (PA[4:1]) matches
PRTAD[4:1]. The LSB of PHY address field (PA[0]) will determine which channel/port within TLK6002 to respond to.
PRTAD[0] is not used functionally, but is present for device testability and compatibility with other devices in the
family of products.
Channel A responds to port address 0 within the block of two port addresses.
Channel B responds to port address 1 within the block of two port addresses.
PRTAD[0] should be grounded on the application board.
The PRTAD[3] pin in application mode should be biased with a pull up or pull down resistor (or allow for an isolation
mechanism from the on board driver), and not connected directly to a power or ground plane. The application board
should allow the flexibility of easily reworking the PRTAD[3] signal to a high level if device debug is necessary (by
including an uninstalled resistor to VDDO1).
Input
LVCMOS
1.5V/1.8V
VDDO3
Low True Device Reset. When asserted (low logic level), this signal resets the entire TLK6002 device. RESET_N
must be held asserted for at least 10 µS after device power stabilization.
Input
LVCMOS
w/Hysteresi
s 1.5V/1.8V
VDDO3
MDIO clock input. Clock input for the Clause 22 MDIO interface.
Note that an external pullup is generally not required on MDC.
Input/
Output
LVCMOS
1.5V/1.8V
VDDO3 25Ω
Driver
MDIO data I/O. MDIO interface data input/output signal for the Clause 22 MDIO interface.
This signal must be externally pulled up to VDDO3, using a 2 kΩ resistor.
During device reset (RESET_N asserted low) this pin is floating. During software initiated power down the
management interface remains active for control register writes and reads. Certain status bits are not deterministic
as their generating clock source may be disabled as a result of asserting either power down input signal. During pin
based power down (PD_TRXA_N and PD_TRXB_N asserted low), this pin is floating. During register based power
down (1.15 asserted high both channels), this pin is driven normally.
Input/
Output
LVCMOS
1.5V/1.8V
VDDO1 25Ω
Driver
SPI Clock (SPI_CLK). Defaults to Output, Driven Low. Can be used as a SPI interface or a generic customer
controllable I/O interface. When used as part of the SPI interface, this signal is the SPI clock to be used with
external TI Jitter cleaner or clock Distribution device.
Three register bits (15.14:12) control this I/O signal. See the detailed register bit description for operational detail.
If unused in the application, this signal can be left floating.
Careful programming is required to prevent accidental contention with simultaneous external drivers. During device
reset (RESET_N asserted low) this pin is driven low. During pin based power down (PD_TRXA_N and PD_TRXB_N
asserted low), this pin is floating. During register based power down (1.15 asserted high both channels), these pins
are driven per register setting
Input/
Output
LVCMOS
1.5V/1.8V
VDDO1 25Ω
Driver
SPI Data. Defaults to Input. Can be used as a SPI interface or a generic customer controllable I/O interface. When
used as part of the SPI interface, this signal is the SPI data from the external TI Jitter cleaner or clock Distribution
device to the TLK6002.
Three register bits (15.10:8) control this I/O signal. See the detailed register bit description for operational detail.
If unused in the application, this signal should be pulled to ground. Careful programming is required to prevent
accidental contention with simultaneous external drivers.
During device reset (RESET_N asserted low) this pin is floating. During pin based power down (PD_TRXA_N and
PD_TRXB_N asserted low), this pin is floating. During register based power down (1.15 asserted high both
channels), these pins are driven per register setting.
Input/
Output
LVCMOS
1.5V/1.8V
VDDO1 25Ω
Driver
SPI Data. Defaults to Output, driven low. Can be used as a SPI interface or a generic customer controllable I/O
interface. When used as part of the SPI interface, this signal is the SPI data from TLK6002 to the external TI Jitter
cleaner or clock Distribution device.
Three register bits (15.6:4) control this I/O signal. See the detailed register bit description for operational detail.
If unused in the application, this signal can be left floating.
Careful programming is required to prevent accidental contention with simultaneous external drivers. During device
reset (RESET_N asserted low) this pin is driven low.
During pin based power down (PD_TRXA_N and PD_TRXB_N asserted low), this pin is floating. During register
based power down (1.15 asserted high both channels), these pins are driven per register setting.
Input/
Output
LVCMOS
1.5V/1.8V
VDDO1 25Ω
Driver
SPI Chip Select. Defaults to Output, Driven High. Can be used as a SPI interface or a generic customer
controllable I/O interface. When used as part of the SPI interface, this signal is the chip select for the external TI
Jitter cleaner or clock Distribution device. Low=Select Device. High=Device Not Selected.
Three register bits (15.2:0) control this I/O signal. See the detailed register bit description for operational detail.
If unused in the application, this signal can be left floating. Careful programming is required to prevent accidental
contention with simultaneous external drivers.
During device reset (RESET_N asserted low) this pin is driven high. During pin based power down (PD_TRXA_N
and PD_TRXB_N asserted low), this pin is floating. During register based power down (1.15 asserted high both
channels), these pins are driven per register setting.
12
Description
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