TLK6002 Datasheet, PDF (51/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

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BIT(s)
6.15
Address: 0x06
NAME
RXCLK_OUT_EN
6.14:12 TX_FIFO_DEPTH[2:0]
6.11 GPI_OVERLAY
6.10 LOS_OVERLAY
6.9 CH_SYNC_OVERLAY
6.8 PLL_LOCK_OVERLAY
6.7 RX_CHAR_CTRL_GPI1
6.6 RX_CHAR_CTRL_LOS
6.5 RX_CHAR_CTRL_CH_SYNC
6.4 RX_CHAR_CTRL_PLL_LOCK
6.3 INVALID_CODE_OVERLAY
6.2 HSTL_SLEW_RATE
6.1:0 HSTL_TERM[1:0]
TLK6002
SLLSE34 – MAY 2010
Table 3-11. OVERRIDE_CONTROL
Default: 0xC000
DESCRIPTION
0 = Holds parallel output clock RXCLK_x output fixed at zero.
1 = Allows RXCLK_x output to toggle normally. (Default 1’b1)
TX FIFO Latency Control (Default 3’b100) This selection allows TX FIFO crash immunity to
be traded off against datapath latency. Selecting a large latency allows for the most dynamic
phase variation between TXCLK_A/B and the selected SERDES channel reference clock
(REFCLK_0/1_P/N). Careful consideration should be made in selecting this value based on
the anticipated phase movement between TXCLK_A/B and selected REFCLK_0/1_P/N
during system operation to avoid unwanted reoccurring transmit FIFO collision.
ACCESS
RW
RW
TX_FIFO_DEPTH
[2:0]
TXCLK_A/B and selected
REFCLK_0/1_P/N. Relative
Phase Movement Allowed
(Serial Bit Times)
000
±4
001
±14
010
±34
011
±54
1xx (Auto Selection)
Full Rate: Same as 011
Half Rate: Same as 010
Quarter Rate: Same as 001
Eighth Rate: Same as 000
Appendix D Datapath Latency
Maximum Value (Serial Bit
Times)
Same
Same +20
Same +60
Same +110
Consistent with above four
selections.
0 = LOSx pin does not reflect GPI1 input signal status (Default 1’b0)
RW
1 = Allows inverse value of GPI1 input signal to be reflected on LOSx pin
0 = LOSx pin does not reflect Serdes Rx Loss of signal condition (Default 1’b0)
RW
1 = Allows Serdes Rx Loss of signal condition to be reflected on LOSx pin
0 = LOSx pin does not reflect loss of channel synchronization status (Default 1’b0)
RW
1 = Allows channel loss of synchronization to be reflected on LOSx pin
0 = LOSx pin does not reflect loss of PLL lock status (Default 1’b0)
RW
1 = Allows loss of PLL lock status to be reflected on LOSx pin
Receive data replacement control when GPI1 input is low
RW
0 = Data passed through as received (Default 1’b0)
1 = Data replaced with K30.7 (when decoder is enabled) or all 0’s (when decoder is disabled)
Receive data replacement control during Loss of signal condition
RW
0 = Data passed through as received (Default 1’b0)
1 = Data replaced with K30.7 (when decoder is enabled) or all 0’s (when decoder is disabled)
Receive data replacement control during Loss of synchronization condition
RW
0 = Data passed through as received (Default 1’b0)
1 = Data replaced with K30.7 (when decoder is enabled) or all 0’s (when decoder is disabled)
Receive data replacement control during Loss of PLL Lock condition
RW
0 = Data passed through as received (Default 1’b0)
1 = Data replaced with K30.7 (when decoder is enabled) or all 0’s (when decoder is disabled)
0 = LOSx pin does not reflect invalid code word error (Default 1’b0)
RW
1 = Allows invalid code word error to be reflected on LOSx pin
Slew Rate setting for RX parallel outputs
RW
0 = No slew control (fastest edge) (Default 1’b0)
1 = 33% slower slew control
Parallel Input Termination setting for TX parallel inputs
RW
00 = Termination disable (High Impedance) (Default 2’b00)
01 = Half termination strength (200 Ω to VHSTL and GND) – Thevenin equivalent of 100 Ω to
(VDDQA/B)/2
1x = Full termination strength (100 Ω to VHSTL and GND) – Thevenin equivalent of 50 Ω to
(VDDQA/B)/2.
Copyright © 2010, Texas Instruments Incorporated
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