TLK6002 Datasheet, PDF (81/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
www.ti.com
SLLSE34 – MAY 2010
• Periodically Check Device Operational Mode Status (Non-Errored Read Values Shown Below):
– Read 5 CHANNEL_STATUS_1 and verify the following bits:
• 5.14 AZ_DONE (1’b1) (per channel)
• 5.13 AGC_LOCKED (1’b1) (per channel)
• 5.9 ENCODE_INVALID (1’b0) (per channel)
• 5.8 DECODE_INVALID (1’b0) (per channel)
• 5.7 TX_FIFO_UNDERFLOW (1’b0) (per channel)
• 5.6 TX_FIFO_OVERFLOW (1’b0) (per channel)
• 5.5 RX_FIFO_UNDERFLOW (1’b0) (per channel)
• 5.4 RX_FIFO_OVERFLOW (1’b0) (per channel)
• 5.2 LOS (1’b0) (per channel). This read value is only useful if the serial input is guaranteed to
be above 150mVdfpp.
• 5.1 CHANNEL_SYNC (1’b1) (per channel)
• 5.0 PLL_LOCK (1’b1) (per channel)
– Read 14.15:0 ERROR_COUNTER[15:0] and verify it is 0 (per channel)
4.19 JITTER TEST PATTERN GENERATION AND VERIFICATION PROCEDURES
Use one of the following procedures to generate and verify the respective test patterns. It is assumed that
an appropriate external cable has been connected between serial outputs and serial inputs. No external
parallel side connections are necessary.
4.19.1 IEEE802.3 Clause 36A Based Continuous Random Pattern (CRPAT) Long/Short
Test Pattern:
• Reset Device:
– Issue a hard or soft reset (RESET_N asserted –or- Write 1 to 0.15 GLOBAL_RESET)
• Select SERDES Reference Clock Input:
– If REFCLK_0_P/N used - Ensure REFCLK_A_SEL (or REFCLK_B_SEL if channel B is used)
primary input pin is low
– If REFCLK_1_P/N used - Ensure REFCLK_A_SEL (or REFCLK_B_SEL if channel B is used)
primary input pin is high
• Ensure a legal reference clock operation frequency is selected based on Appendix B (Continuous Rate
Device Configuration), and provision CHANNEL_CONTROL_1 register accordingly.
• Serial Configuration
– Configure the following bits per the desired application:
• 1.9:8 (LOOP_BANDWIDTH[1:0])
• 2.12:8 (TWPOST1[4:0])
• 2.7:4 (TWPRE[3:0])
• 2.3:0 (SWING[3:0])
• 8.14:12 (EQPRE[2:0])
• 8.11:10 (CDRTHR[1:0]) = 2’b01
• 8.9:8 (CDRFMULT[1:0]) = 2’b00
• 1.3:0 PLL_MULT[3:0]
• 1.7:6 RATE_TX[1:0] (CRPAT supported only in half/quarter/eighth rate modes
• 1.5:4 RATE_RX[1:0] (CRPAT supported only in half/quarter/eighth rate modes).
• Check SERDES PLL Status for Locked State
– Poll 5.0 PLL_LOCK (per channel) until it is asserted (high).
• Toggle ENRX
– Write 1’b0 to 20.2 (ENRX)
Copyright © 2010, Texas Instruments Incorporated
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