TLK6002 Datasheet, PDF (44/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
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3 PROGRAMMERS REFERENCE
The following registers can be addressed directly through Clause 22. Channel identification is based on
PHY (Port) address field. Registers 0x01- 0x0C, 0X14 are per channel basis.
Channel A can be accessed by setting LSB of PHY address to 0.
Channel B can be accessed by setting LSB of PHY address to 1.
Table 3-1. GLOBAL_CONTROL_1
Address: 0x00
Default: 0x0600
BIT(s)
NAME
DESCRIPTION
ACCESS
0.15 GLOBAL_RESET
Global reset (Channel A and B).
0 = Normal operation (Default 1’b0)
RW
SC ⁽¹⁾
1 = Resets TX and RX datapath including MDIO registers. Equivalent to asserting
RESET_N.
0.11 GLOBAL_WRITE
Global write enable.
RW
0 = Control settings written to Registers 0x01-0x0C, 0x14 are specific to channel
addressed (Default 1’b0)
1 = Control settings written to Registers 0x01-0x0C, 0x14 are applied to both Channel A
and Channel B regardless of channel addressed
0.10:8 HSTL_IMPED_CLK_DIV[2: HSTL Impedance Control clock divide selection.
RW
0]
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64 (Default 3’b110)
111 = Divide by 128
This value, in tandem with register bit 0.7, selects the frequency and source of the clock
used for dynamic voltage, temperature, and impedance compensation in the HSTL I/O
buffers. The division value selected should yield a value less than 10 MHz, and is
calculated by dividing the selected REFCLK_0/1_P/N frequency by the value above.
0.7 HSTL_IMPED_CLK_SEL HSTL Impedance Control reference clock source selection.
RW
0 = Selects channel A reference clock (as selected by REFCLK_A_SEL) as clock
reference to HSTL impedance control (Default 1’b0)
1 = Selects channel B reference clock (as selected by REFCLK_B_SEL) as clock
reference to HSTL impedance control
See register bit 0.10:8 for further details.
0.6 CLKOUT_SEL
Output clock select. Selected RXBCLK_A/B or ARS output clock is sent out on
RW
CLK_OUT_P/N pins . Logically OR’ed with CLK_OUT_SEL pin.
0 = Selects Channel A recovered byte clock (RXBCLK_A) as output clock (Default 1’b0)
1 = Selects Channel B recovered byte clock (RXBCLK_B) as output clock.
See Figure 1-3
0.5:4 CLKOUT_DIV[1:0]
Output clock divide setting in non-ARS mode.This value is used to divide selected
RW
RXBCLK before giving it out onto CLK_OUT_P/N.
CLK_OUT_P/N Frequency = (Serial Bit Rate / 10)/(Register 0.5:4 Setting)
00 = Divide by 1 (Default 2’b00)
01 = Divide by 2
10 = Divide by 4
11 = Divide by 8
See Table 2-9 and Figure 1-3
(1) After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle.
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PROGRAMMERS REFERENCE
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