TLK6002 Datasheet, PDF (73/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
www.ti.com
SLLSE34 – MAY 2010
4.13 HSTL (SDR Timing Mode Only) Input Timing Requirements
t_setupH
t_holdH
t_setupL
t_holdL
t_duty
t_period
PARAMETER
TDx⁽¹⁾ setup prior to TXCLK_x⁽²⁾ transition
high
TDx hold after TXCLK_x transition high
TDx setup prior to TXCLK_x transition low
TDx hold after TXCLK_x transition low
TXCLK_x Duty Cycle
TXCLK_x Period
CONDITION
Falling Edge Aligned (Rising Edge Sampled) Data,⁽³⁾ See
Figure 4-18
Rising Edge Aligned (Falling Edge Sampled) Data,⁽³⁾ See
Figure 4-19
Rising and Falling Edge Sampled Data
Rising and Falling Edge Aligned Data
T_freq
TXCLK_x Frequency
Rising and Falling Edge Aligned Data
(1) TDx refers to either channel A (TDA) or B (TDB).
(2) TXCLK_x refers to either channel A (TXCLK_A) or channel B (TXCLK_B).
(3) Input timing reference of (VDDQA/B)/2 with ±1 ns/V rise time on all input signals.
MIN MAX UNIT
480
ps
480
480
480
40%
3.2
23.5
60%
42.5
5
312.
5
ps
ps
ps
ns
MHz
TXCLK_x
V_IH(ac)
TDx _VDDQ/2
V_IL(ac)
t_PERIOD
t_SETUPH t_HOLDH
V_IH(ac)
VDDQ/2
V_IL(ac)
Figure 4-18. HSTL (SDR Timing Mode Only) Falling Edge Aligned (Rising Edge Sampled) Data Input
Timing Requirements
TXCLK_x
V_IH(ac)
TDx ^VDDQ/2
V_IL(ac)
t_PERIOD
t_SETUPL t_HOLDL
V_IH(ac)
VDDQ/2
V_IL(ac)
Figure 4-19. HSTL (SDR Timing Mode Only) Rising Edge Aligned (Falling Edge Sampled) Data Input
Timing Requirements
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