TLK6002 Datasheet, PDF (21/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
www.ti.com
SLLSE34 – MAY 2010
Figure 2-1 shows the two modes of operation in SDR mode, rising edge aligned mode and falling edge
aligned mode. In rising edge aligned mode, TDA_* and TDB_* inputs are sampled on the falling edges of
TXCLK_A and TXCLK_B respectively. In falling edge aligned mode, TDA_* and TDB_* inputs are
sampled on the rising edge of TXCLK_A and TXCLK_B respectively. In rising edge aligned mode, RDA_*
and RDB_* are timed such that an external device can sample the data using the falling edge of
RXCLK_A and RXCLK_B respectively. In falling edge aligned mode, RDA_* and RDB_* are timed such
that an external device can sample the data using the rising edge of RXCLK_A and RXCLK_B
respectively.
2.6 20-bit DDR (Double Data Rate) Mode (8b/10b Encoder/Decoder Disabled)
When DDR is enabled with the 8b/10b encoder disabled, the data format is identical to that of "20-bit SDR
(Single Data Rate) Mode (8b/10b Encoder/Decoder Disabled)" mode, except that four symbols are
transferred per parallel interface clock cycle instead of two. See the referenced previous section for further
details. Figure 2-3 shows the two modes of operation in DDR mode, source centered and source aligned
mode. In source centered mode, TDA_* and TDB_* inputs are sampled on the rising and falling edges of
TXCLK_A and TXCLK_B respectively. In source aligned mode, TDA_* and TDB_* inputs arrive
simultaneously with TXCLK_A and TXCLK_B respectively, and the TXCLK_A and TXCLK_B sampling
window is created internal to TLK6002 by delaying the clock. In source centered mode, RDA_* and RDB_*
are timed such that an external device can sample the data using RXCLK_A and RXCLK_B respectively,
where the appropriate timing window for sampling is created by TLK6002. In source aligned mode, RDA_*
and RDB_* are aligned with RXCLK_A and RXCLK_B respectively at the outputs of TLK6002, and the
sampling window must be created external to TLK6002.
DDR Source Centered Timing
TXCLK _A/B
TDA /B_[19 :0]
Data 0[ 19:0]
Data 1[ 19:0]
RXCLK _A /B
RDA /B_[19 :0]
Data 0[ 19:0]
Data 1[ 19:0]
TXCLK _A/B
TDA /B_[19 :0]
DDR Source Aligned Timing
Data 0[ 19:0]
Data 1[ 19:0]
RXCLK _A /B
RDA /B_[19 :0]
Data 0[ 19:0]
Data 1[ 19:0]
Figure 2-3. 20-bit DDR Parallel Interface Mode
Copyright © 2010, Texas Instruments Incorporated
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