TLK6002 Datasheet, PDF (34/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
www.ti.com
that greater than 4.5 seconds of time can be programmed per attempted interval. Thus, the ARS state
machine will attempt to determine a particular serial rate for a programmable number of reference clock
periods where channel synchronization cannot be established before attempting the next (and different)
lower serial bit rate, in a repeating/looping fashion when the lowest enabled serial bit rate is attempted
unsuccessfully.
The ARS function overrides the following SERDES register settings (RATE_TX / RATE_RX / PLL_MULT).
MDIO writes to these registers do not impact the actual values controlling internal SERDES device
settings as long as ARS is enabled for that channel, and reads instead return the current settings (which
may or may not be valid) as controlled by the ARS state machine (and does so until ARS is disabled).
Table 2-7. ARS Looped Device Settings (Looping order highest → lowest enabled bit rate)
ARS Rate / Scale / Multiplier Settings Per Reference Clock
Standard
CPRI
OBSAI
CPRI
OBSAI
CPRI
CPRI/OBSAI
CPRI
CPRI/OBSAI
Serial Rate (Gbps)
0.6144
0.768
1.2288
1.536
2.4576
3.072
4.9152
6.144
Rate
Eighth
Eighth
Quarter
Quarter
Half
Half
Full
Full
Rate Scale
4
4
2
2
1
1
0.5
0.5
Reference Clock (MHz)
153.6
122.88
307.2
SERDES Multiplier Setting Loop
16
20
8
20
25
10
16
20
8
20
25
10
16
20
8
20
25
10
16
20
8
20
25
10
34
Description
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