TLK6002 Datasheet, PDF (82/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
www.ti.com
– Write 1’b1 to 20.2 (ENRX)
• Select Test Pattern:
– If CRPAT Long Pattern is desired:
• Write 3’b011 to 7.10:8 TEST_PATTERN_SEL[2:0]
– If CRPAT Short Pattern is desired:
• Write 3’b100 to 7.10:8 TEST_PATTERN_SEL[2:0]
• Enable Test Pattern Generation:
– Write 1’b1 to 7.13 TP_GEN_EN
– Poll 5.13 AGC_LOCKED (1’b1) (per channel)
• Final CDR Configuration
– Wait until either AGC_LOCKED asserted or 250M UI
– Write 8.9:8 (CDRFMULT[1:0]) = 2’b01
– Poll 5.13 AGC_LOCKED (1’b1) (per channel)
• Issue Data path Reset
– Write 1’b1 to 4.3 DATAPATH_RESET
• Enable Test Pattern Verification:
– Write 1’b1 to 7.12 TP_VERIFY_EN
• Clear Counters:
– Read 14.15:0 ERROR_COUNTER[15:0] and discard the value.
• Verify Test In Progress:
– Poll 5.12 TP_STATUS until asserted.
• The pattern verification is now in progress.
• Verify Error Free Operation (as many times as desired during the duration of the test period):
– Read 14.15:0 ERROR_COUNTER[15:0], and verify 16’h0000 is read to confirm error free
operation.
If more than one test is specified results are unpredictable.
If another test type is desired, begin at the first step of that procedure.
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ELECTRICAL SPECIFICATIONS
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