TLK6002 Datasheet, PDF (50/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
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Table 3-9. CHANNEL_CONTROL_4
Address: 0x04
Default: 0x0000
BIT(s)
NAME
DESCRIPTION
ACCESS
4.3 DATAPATH_RESET
Channel datapath reset control. Required once the desired functional mode is configured.
0 = Normal operation. (Default 1’b0)
RW
SC ⁽¹⁾
1 = Resets channel logic excluding MDIO registers. (Resets both Tx and Rx datapath)
4.2 TXFIFO_RESET
Transmit FIFO reset control
0 = Normal operation. (Default 1’b0)
1 = Resets transmit datapath FIFO.
4.1 RXFIFO_RESET
Receive FIFO reset control
0 = Normal operation. (Default 1’b0)
1 = Resets receive datapath FIFO.
(1) After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle.
Table 3-10. CHANNEL_STATUS_1
Address: 0x05
BIT(s)
NAME
5.14 AZ_DONE
5.13 AGC_LOCKED
5.12 TP_ STATUS
5.11 ARS_PLL_LOCK_ERROR
5.10 ARS_LOCKED
5.9 ENCODE_INVALID
5.8 DECODE_INVALID
5.7 TX_FIFO_UNDERFLOW
5.6 TX_FIFO_OVERFLOW
5.5 RX_FIFO_UNDERFLOW
5.4 RX_FIFO_OVERFLOW
5.3 GPI1
5.2 LOS
5.1 CHANNEL_SYNC
5.0 PLL_LOCK
Default: 0x0000
DESCRIPTION
Auto zero complete indicator.
When high, indicates auto zero calibration is complete
Adaptive gain control loop lock indicator.
When high, indicates AGC loop is in locked state
Test Pattern status for test pattern selected in 7.10:8 .
0 = Alignment has not achieved
1 = Alignment has been determined and correct pattern has been received.
Any bit errors received are reflected in ERROR_COUNTER register (0x0E)
ARS PLL Lock error indicator. Valid only when ARS function is enabled.
When high, indicates ARS did not detect PLL lock within the time specified through
ARS_INTERVAL[20:0] (11.4:0,12.15:0).
ARS lock indicator. Valid only when ARS function is enabled.
When high, indicates ARS has determined incoming serial data rate.
Valid in 16 bit (SDR/DDR) mode (encoder enabled) and during
CRPAT test pattern generation.
When high, indicates encoder received an invalid control word.
Valid in 16 bit (SDR/DDR) mode (decoder enabled) and during CRPAT test pattern
verification.
When high, indicates decoder received an invalid code word, or a 8b/10b disparity error.
In functional mode, number of DECODE_INVALID errors are reflected in
ERROR_COUNTER register (0x0E)
When high, indicates underflow has occurred in the transmit datapath FIFO.
When high, indicates overflow has occurred in the transmit datapath FIFO.
When high, indicates underflow has occurred in the receive datapath FIFO.
When high, indicates overflow has occurred in the receive datapath FIFO.
GPI1 status Indicator.
Reflects GPI1 input signal status.
Loss of Signal Indicator.
When high, indicates that a loss of signal condition is detected on serial receive inputs
Channel synchronization status indicator. Valid only when comma detection is enabled
When high, indicates channel synchronization has achieved
Serdes PLL lock indicator
When high, indicates Serdes PLL is locked to the selected incoming REFCLK_0/1_P/N
ACCESS
RO/LL
RO
RO/LH
RO/LL
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO
RO/LH
RO/LL
RO/LL
50
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