TLK6002 Datasheet, PDF (13/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
www.ti.com
SLLSE34 – MAY 2010
Terminal
Signal
BGA
TDI
R15
TDO
R14
TMS
R3
TCK
T16
TRST_N
T3
TESTEN
T17
GPI0
R4
GPI1
K10
AMUXA
U5
AMUXB
V14
RESRA,
K8
RESTA,
M1
RESRB,
J14
RESTB
M18
Table 2-1. Pin Description – Signal Pins (continued)
Direction
Type
Supply
Description
Input
LVCMOS
1.5V/1.8V
VDDO2
(Internal
Pullup)
JTAG Input Data. TDI is used to serially shift test data and test instructions into the device during the operation of
the test port. In system applications where JTAG is not implemented, this input signal may be left floating.
During pin based power down (PD_TRXA_N and PD_TRXB_N asserted low), this pin is not pulled up. During
register based power down (1.15 asserted high both channels), this pin is pulled up normally.
Output
LVCMOS
1.5V/1.8V
VDDO2 50Ω
Driver
JTAG Output Data. TDO is used to serially shift test data and test instructions out of the device during operation of
the test port. When the JTAG port is not in use, TDO is in a high impedance state.
During device reset (RESET_N asserted low) this pin is floating. During pin based power down (PD_TRXA_N and
PD_TRXB_N asserted low), this pin is floating. During register based power down (1.15 asserted high both
channels), this pin is floating.
Input
LVCMOS
1.5V/1.8V
VDDO3
(Internal
Pullup)
JTAG Mode Select. TMS is used to control the state of the internal test-port controller. In system applications
where JTAG is not implemented, this input signal can be left unconnected.
During pin based power down (PD_TRXA_N and PD_TRXB_N asserted low), this pin is not pulled up. During
register based power down (1.15 asserted high both channels), this pin is pulled up normally.
Input
LVCMOS
w/Hysteresi
s 1.5V/1.8V
VDDO2
JTAG Clock. TCK is used to clock state information and test data into and out of the device during boundary scan
operation. In system applications where JTAG is not implemented, this input signal should be grounded.
Input
LVCMOS
1.5V/1.8V
VDDO3
(Internal
Pulldown)
JTAG Test Reset. TRST_N is used to reset the JTAG logic into system operational mode. This input can be left
unconnected in the application and is pulled down internally, disabling the JTAG circuitry. If JTAG is implemented
on the application board, this signal should be deasserted (high) during JTAG system testing, and otherwise
asserted (low) during normal operation mode.
During pin based power down (PD_TRXA_N and PD_TRXB_N asserted low), this pin is not pulled down. During
register based power down (1.15 asserted high both channels), this pin is pulled down normally.
Input
LVCMOS
1.5V/1.8V
VDDO2
Test Enable. This signal is used during the device manufacturing process. It should be grounded through a resistor
in the device application board. The application board should allow the flexibility of easily reworking this signal to a
high level if device debug is necessary (by including an uninstalled resistor to VDDO2).
Input
LVCMOS
1.5V/1.8V
VDDO3
General Purpose Input Zero. This signal is used during the device manufacturing process. It should be grounded
through a resistor on the device application board. The application board should also allow the flexibility of easily
reworking this signal to a high level if device debug is necessary (by including an uninstalled resistor to VDDO3).
Input
LVCMOS
1.5V/1.8V
VDDO1
General Purpose Input One. This signal can be used to logically combine an external status condition with LOSA
or LOSB if enabled in an mdio register. Note that if GPI1 is low, LOSA/B will be asserted if logical combination is
enabled. Similarly, if GPI1 is high, LOSA/B will be deasserted. If unused, this input should be grounded in the
device application (not floating).
Analog I/O
SERDES Channel A Analog Testability I/O. This signal is used during the device manufacturing process. It should
be left unconnected in the device application.
Analog I/O
SERDES Channel B Analog Testability I/O. This signal is used during the device manufacturing process. It should
be left unconnected in the device application.
Analog
Input
HSTL Impedance Matching Resistors. These resistors are used as a reference for internal terminations on the
HSTL inputs and outputs. Each RES* pin requires it’s own resistor, sharing resistors between RES* pins is not
possible. A 50 ohm 0.5% tolerance resistor should be selected to guarantee device datasheet specified parallel
interface timing specification.
Copyright © 2010, Texas Instruments Incorporated
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Description
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