TLK6002 Datasheet, PDF (88/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
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6 Appendix B – Continuous Rate Device Configuration
The REFCLK needed based on a particular SERDES configuration is as follows:
SERDES Reference Clock = (Rate Scale) × (Serial Bit Rate) / (Serdes Multiplier)
Note that Table 6-1 indicates legal ranges for each setting.
Table 6-1. Continuous Rate SERDES Configuration Settings
SERDES Serial Rate Configuration
SERDES Reference Clock
Serial Rate (Gbps)
SERDES
Multiplier
Period (ns)
Min
Max
Frequency
(MHz)
Max Min
Full
Max Max
Half
Min Max
Quarter
Max Min
Eighth
Max Max
4
1.25
2.14
800
467
3.74 6.25 1.87 3.20 0.93 1.60 0.47 0.80
5
1.33
2.67
752
375
3.75 6.25 1.87 3.76 0.94 1.88 0.47 0.94
6
1.6
3.2
625
313
3.75 6.25 1.88 3.75 0.94 1.88 0.47 0.94
8
2.13
4.26
469
235
3.76 6.25 1.88 3.76 0.94 1.88 0.47 0.94
8.25
2.19
4.4
457
227
3.75 6.25 1.88 3.77 0.94 1.88 0.47 0.94
10
2.67
5.33
375
188
3.75 6.25 1.88 3.75 0.94 1.87 0.47 0.94
12
3.2
6.4
313
156
3.75 6.25 1.88 3.75 0.94 1.88 0.47 0.94
15
4
8.14
250 122.88 3.69 6.25 1.84 3.75 0.92 1.88 0.46 0.94
16
4.25
8.14
235 122.88 3.93 6.25 1.97 3.76 0.98 1.88 0.49 0.94
16.5
4.39
8.14
228 122.88 4.06 6.25 2.03 3.76 1.01 1.88 0.51 0.94
20
5.33
8.14
188 122.88 4.92 6.25 2.46 3.75 1.23 1.88 0.61 0.94
25
6.67
8.14
150 122.88 6.14 6.25 3.07 3.75 1.54 1.87 0.77 0.94
Note: In Full Rate Mode, the SERDES Reference Clock range shown above must be limited such that serial side operation does not exceed
6.25 Gbps.
Rate Scale
Full
Half
Quarter
Eighth
0.5
1
2
4
Serial performance is optimal when the highest reference clock and lowest SERDES multiplier is chosen
for a given application rate.
88
Appendix B – Continuous Rate Device Configuration
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