TLK6002 Datasheet, PDF (41/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
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SLLSE34 – MAY 2010
Table 2-10. MDIO Related Signals
SIGNAL
MDC
MDIO
PRTAD[4:0]
TYPE
DESCRIPTION
LVCMOS
1.5V/1.8V
Input VDDO3
Management Interface Clock. This clock is used to sample the MDIO signal.
LVCMOS
Management Interface Data. Bidirectional data line for MDIO Port is sampled on the rising edge of MDC.
1.5V/1.8V
Input/OutputVDDO3
THIS SIGNAL MUST BE EXTERNALLY PULLED UP TO VDDO3. Consult IEEE802.3 Clause 22 for an appropriate
resistance value.
LVCMOS
1.5V/1.8V
Input
VDDO2/ VDDO1/
VDDO1/ VDDO1/
VDDO1
Port Address. Used to select the Port ID in Clause 22 MDIO mode.
PRTAD[4:1] selects a block of two sequential Clause 22 port addresses. Each channel is implemented as a different port
address, and can be accessed by setting the appropriate port address field within the Clause 22 MDIO transaction.
PRTAD[0] is not used functionally, but is needed for device testability with other devices in the family of products.
Channel A responds to port address 0 within the block of two port addresses.
Channel B responds to port address 1 within the block of two port addresses.
It is possible for 16 TLK6002 devices to logically share an MDIO bus.
In Clause 22, the top 4 control pins PRTAD[4:1] determine the device port address. In this mode the 2
individual channels in TLK6002 are classified as 2 different ports. So for any PRTAD[4:1] value there will
be 2 ports per TLK6002.
TLK6002 will respond if the 4 MSB's of PHY address field on MDIO protocol (PA[4:1]) matches
PRTAD[4:1]. The LSB of PHY address field (PA[0]) will determine which channel/port within TLK6002 to
respond to.
If PA[0] = 1b0, TLK6002 Channel A will respond.
If PA[0] = 1b1, TLK6002 Channel B will respond.
Write transactions which address an invalid register or device or a read only register will be ignored. Read
transactions which address an invalid register will return a 0.
MDIO Protocol Timing:
The Clause 22 timing required to read from the internal registers is shown in Figure 2-9. The Clause 22
timing required to write to the internal registers is shown in Figure 2-10.
MDC
MDIO
Pu1
0 1 1 0 PA4 PA0 RA4 RA0
0 D15 D0 1
32 "1's"
Preamble
Start
Read
Code
Turn
PHY
REG
Around
Data
Idle
Addr
Addr
(1) Note that the 1 in the Turn Around section is externally pulled up, and driven to Z by TLK6002.
Figure 2-15. CL22 – Management Interface Read Timing
MDC
MDIO
0
1
0
1
PA [4:0]
RA4 RA0 1
0 D15 D0 ¹
32 "1's"
Preamble
Start
Write
Code
PHY
Addr
REG
Addr
Turn
Around
Data
Idle
Figure 2-16. CL22 – Management Interface Write Timing
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