TLK6002 Datasheet, PDF (7/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
www.ti.com
SLLSE34 – MAY 2010
2 Description
2.1 Pin Descriptions
Terminal
Signal
BGA
Channel A:
TXAP
V7
TXAN
V6
RXAP
U9
RXAN
U8
TXCLK_A
P1
H1
J3
H2
K4
J2
J1
K5
L3
L5
TDA_[19:0 ]
M3
M4
K3
M5
N3
M2
P2
P4
N5
R2
P5
D1
B3
B1
C2
E2
F2
F3
A2
C3
RDA_[19:0]
D3
C1
F4
D4
E4
G4
G3
H4
E5
H5
G5
Direction
Type
Supply
Table 2-1. Pin Description – Signal Pins
Description
Output
CML
AVDD
Input CML
AVDD
Input HSTL
1.5V/1.8V
VDDQA
Serial Transmit Channel A Output. TXAP and TXAN comprise the transmit direction Channel A differential serial
high speed output signal.
During device reset (RESET_N asserted low) these pins are driven differential zero.
These CML outputs must be AC coupled.
During pin based power down (PD_TRXA_N asserted low), these pins are floating.During register based power
down (1.15 asserted high), these pins are floating.
Serial Receive Channel A Input. RXAP and RXAN comprise the receive direction Channel A differential high
speed serial input signal. These signals must be AC coupled.
Transmit Input Channel A Clock. TXCLK_A is used to sample Channel A input parallel data (TDA_[19:0]).
This input must be synchronous (0 ppm) to the SERDES reference clock.
In SDR mode, this signal is equal in frequency to serial bit rate / 20.
In DDR mode, this signal is equal in frequency to serial bit rate / 40.
If unused in the application, this input must be grounded.
Parallel Input Channel A Transmit Data Bus.
These data signals are synchronous to and sampled by TXCLK_A.
Input
HSTL
1.5V/1.8V
VDDQA
Output
HSTL
1.5V/1.8V
VDDQA
Two data modes are supported, SDR (Single Data Rate), and DDR (Double Data Rate). SDR has two valid symbols
per TXCLK_A cycle, and DDR has four valid symbols per TXCLK_A cycle.
When input data is in 8b/10b encoded format (a.k.a. 20-bit data mode), TDA_[19:10] and TDA_[9:0] each carry a
symbol.
When input data is encoded internal to TLK6002 (8b/10b encoder enabled, a.k.a. 16-bit data mode), two symbols
are input at a time, defined as follows:
One Symbol – TDA_[8] contains the control bit (k-character indication) of data byte TDA_[7:0], and TDA_[9] is
unused and should be grounded.
Other Symbol – TDA_[18] contains the control bit (k-character indication) of data byte TDA_[17:10], and TDA_[19] is
unused and should be grounded.
Unused parallel input pins must be grounded.
See the following figures for more detail:
Figure 2-1 20-bit SDR Parallel Interface Mode.
Figure 2-2 16-bit SDR Parallel Interface Mode.
Figure 2-3 20-bit DDR Parallel Interface Mode
Parallel Channel A Receive Data Bus.
These output receive data signals are synchronous to RXCLK_A.
Two data modes are supported, SDR (Single Data Rate), and DDR (Double Data Rate). SDR has two valid symbols
per RXCLK_A cycle, and DDR has four valid symbols per RXCLK_A cycle.
When output data is in 8b/10b encoded format (a.k.a. 20-bit data mode), RDA_[19:10] and RDA_[9:0] each carry a
symbol.
When output data is decoded internal to TLK6002 (8b/10b decoder enabled, a.k.a. 16-bit data mode), two symbols
are output at a time, defined as follows:
One Symbol – RDA_[8] contains the control bit (k-character indication) of data byte RDA_[7:0], and RDA_[9]
indicates whether a 8b/10b disparity error was detected or an invalid code was received coincident with that
particular symbol
Other Symbol – RDA_[18] contains the control bit (k-character indication) of data byte RDA_[17:10], and RDA_[19]
indicates whether a 8b/10b disparity error was detected or an invalid code was received coincident with that
particular symbol.
During device reset (RESET_N asserted low) these pins are driven low.During pin based power down
(PD_TRXA_N asserted low), these pins are floating.During register based power down (1.15 asserted high), these
pins are floating.
See the following figures for more detail:
Figure 2-1 20-bit SDR Parallel Interface Mode.
Figure 2-2 16-bit SDR Parallel Interface Mode.
Figure 2-3 20-bit DDR Parallel Interface Mode.
Copyright © 2010, Texas Instruments Incorporated
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Description
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