TLK6002 Datasheet, PDF (72/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
www.ti.com
4.12 HSTL (DDR Timing Mode Only) Input Timing Requirements
t_setup
t_hold
PARAMETER
TDx⁽¹⁾ setup prior to TXCLK_x⁽²⁾ transition high
or low
TDx hold after TXCLK_x transition high or low
t_duty
TXCLK_x Duty Cycle
t_period
T_freq
T_skew ^{(4) (5}
)
TXCLK_x Period
TXCLK_x Frequency
TXCLK_x rising or falling to TDx valid.
CONDITION
Source Centered, See Figure 4-16
and ⁽³⁾
Source Centered, See Figure 4-16
and ⁽³⁾
Source Centered, See Figure 4-16
and ⁽³⁾
Source Aligned, See Figure 4-17
and ⁽³⁾
Source Centered and Aligned
Source Centered and Aligned
Source Aligned, See Figure 4-17
and ⁽³⁾
(1) TDx refers to either channel A (TDA) or B (TDB).
(2) TXCLK_x refers to either channel A (TXCLK_A) or channel B (TXCLK_B).
(3) Input timing reference of (VDDQA/B)/2 with ±1 ns/V rise time on all input signals.
(4) When T_freq ≤60 MHz, Tskew Minimum is –3ns.
(5) When T_freq ≤60 MHz, Tskew Maximum is 3ns.
MIN
0.075 × t_period
0.075 × t_period
40%
45%
6.4
11.75
–0.14 × t_period
MAX
60%
55%
85.11
156.25
+0.14 × t_period
UNIT
ps
ps
ns
MHz
ps
TXCLK_x
V_IH(ac)
TDx
VDDQ/2
V_IL(ac)
t_PERIOD
t_SETUP t_HOLD
t_SETUP
V_IH(ac)
VDDQ/2
V_IL(ac)
t_HOLD
Figure 4-16. HSTL (DDR Timing Mode Only) Source Centered Data Input Timing Requirements
TXCLK_x
V_OH(ac)
TDx _VDDQ/2
V_OL(ac)
T_SKEW
T_SKEW
V_OH(ac)
VDDQ/2
V_OL(ac)
Figure 4-17. HSTL (DDR Timing Mode Only) Source Aligned Data Input Timing Requirements
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ELECTRICAL SPECIFICATIONS
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