TLK6002 Datasheet, PDF (5/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
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CLK_OUT_P/N
CLK_OUT_SEL
REFCLK_A_SEL
REFCLK_0_P/N
REFCLK_1_P/N
REFCLK_B_SEL
ARS
Control /
Divider
Incoming Serial Bit Rate *(1/2/4/8 Full/Half/Quarter/Eighth) / 4
Incoming Serial Bit Rate *(1/2/4/8 Full/Half/Quarter/Eighth) / 4
1
1/N
0
0.5:4
S/W
0.6
S/W
0.1
-
0
1
0
-
1
S/W
0.0
RXDA[9:0]
RXBCLK_A ^RX
TXDA[9:0]
TXBCLK_A ^TX
ARS Channel A
ARS Channel B
RXDB[9:0]
RXBCLK_B
RX
TXDB[9:0]
TXBCLK_B ^TX
Channel A
SERDES
REFCLKP/N
REFCLKP/N
Channel B
SERDES
SLLSE34 – MAY 2010
Note: Also equal in frequency to MPY*REFCLK/2
+
RXAP
-
RXAN
TXAP
TXAN
+
RXBP
-
RXBN
TXBP
TXBN
Legend:
= Primary Device Pin
S/W _{= Software Programmable / Register Address.Bit}
x.x:x
RXBCLK_*, TXBCLK_* frequency is Serial Bit Rate Divided by 10
RXBCLK_* is referred to as the recovered byte clock, and is always
synchronous with the incoming serial data rate (when valid).
Figure 1-3. TLK6002 Reference Clock/Output Clock Architecture
TXCLK_B
TXCLK_A
TDA_[19:0]
A S/W
3.10
TDB_[19:0]
B S/W
3.10
0
1
TXDA_INT[9:0]
CH A TX
TXDA[9:0]
Channel A
1
TX A FIFO
TXBCLK_A
TXDAaDtaaptaatphath
TXBCLK_A
TTXXASDEaRtaDpEaSth
0
TX B FIFO
TXDB_INT[9:0]
TXBCLK_B
CH B TX
TXDAaDtaaptaatphath
TXDB[9:0]
TXBCLK_B
Channel B
TTXXASDEaRtaDpEaSth
0
1
1
0
`
Legend:
= Primary Device Pin
S/W
x.x:x
= Software Programmable / Register Address.Bit
RXBCLK_*, TXBCLK_* frequency is Serial Bit Rate Divided by 10
Figure 1-4. TLK6002 Transmit Clock Architecture
Copyright © 2010, Texas Instruments Incorporated
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Introduction
5