TLK6002 Datasheet, PDF (70/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
Input Jitter Definition
J_DR
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J_R
J_R
J_TOL
NOTE: J_TOL = J_R + J_DR, where J_TOL is the receive jitter tolerance, J_DR is the received deterministic jitter, and J_R is the
Gaussian random edge jitter distribution at a maximum BER = 10^-12 for CPRI link and BER = 10^-15 for OBSAI (RP3)
link.
4.10 HSTL Output Switching Characteristics (DDR Timing Mode Only)
(over recommended operating conditions unless otherwise noted).
t_setup
t_hold
PARAMETER
RDx⁽¹⁾ setup prior to RXCLK_x transition high or
low
RDx hold after RXCLK_x transition high or low
CONDITION
Source Centered. See Figure 4-12⁽²⁾
Source Centered. See Figure 4-12⁽²⁾
T_duty
t_period
T_freq
T_pd
RXCLK_x⁽³⁾ Duty Cycle
RXCLK_x Period
RXCLK_x Frequency
RXCLK_x rising or falling to RDx valid.
Source Centered and Source Aligned.⁽²⁾
Source Centered and Source Aligned.
Source Centered and Source Aligned.
Source Aligned See Figure 4-13⁽²⁾
(1) RDx refers to either RDA or RDB for channels A and B respectively
(2) Cload = 10pF, using timing reference of (VDDQA/B)/2.
(3) RXCLK_x refers to RXCLK_A or RXCLK_B for channels A and B respectively.
MIN
0.15 ×
tperiod
0.15 ×
tperiod
45%
6.4
11.75
–0.10 ×
tperiod
MAX
55%
85.11
156.25
+0.10 ×
tperiod
UNIT
ps
ps
ns
MHz
ps
RXCLK_x
V_OH(ac)
RDx VDDQ/2
V_OL(ac)
t_PERIOD
t_SETUP
t_HOLD t_SETUP
V_OH(ac)
VDDQ/2
V_OL(ac)
t_HOLD
Figure 4-12. HSTL (DDR Timing Mode Only) Source Centered Output Timing Requirements
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ELECTRICAL SPECIFICATIONS
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