TLK6002 Datasheet, PDF (33/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
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SLLSE34 – MAY 2010
Using any one of the three supported reference clock frequencies allows all eight currently defined CPRI
and OBSAI rates to be achieved with a single reference clock frequency, and eliminates the need for
external hardware to support multiple frequencies for OBSAI and CPRI operation. See Table 2-7 for a list
of supported CPRI/OBSAI rates.
ARS can be enabled/disabled through device pins (RATE_A/B) or channel A or B MDIO register bits
(ARS_EN[1:0], register bits 10.13:12), Software control is enabled by setting RATE_A/RATE_B pins to
100. Pin control is enabled by setting RATE_A/B pins to 101/110/111. ARS can be enabled or disabled
independently on each channel.
ARS does not support determination of incoming serial rates other than the eight defined by the
CPRI/OBSAI specifications. ARS should not be enabled unless one of those incoming serial rates is
anticipated. See Table 2-7 for a list of the supported CPRI/OBSAI incoming serial rates.
When ARS is enabled, a state machine will continuously loop through (and override previously
programmed) relevant SERDES control settings for a given input reference clock frequency until either an
incoming serial bit rate is successfully determined (indicated by assertion of channel A or B MDIO register
ARS_LOCKED, register bit 5.10), or the ARS function is disabled (either through device pin or MDIO
software control). Note that the order attempted is always from the highest serial bit rate to the lowest
serial bit rate. There is an MDIO register enable per serial bit rate per channel (ARS_SBR_ENABLE[7:0],
register bit 11.13:6), such that any number between one and eight of the supported incoming serial rates
can be determined. If an incoming serial bit rate is successfully determined, and then subsequently lost,
the state machine will automatically continue searching for a stable rate (as long as ARS is not disabled),
first starting with the last successful rate (if existing, effecting a single retry of the last working rate), and
then continuing down sequentially through the enabled lower serial rates (or if there are none, starting
over with the highest enabled incoming serial rate settings).
The ARS function monitors the incoming 8b/10b encoded serial receive data, using both the comma
character and 8b/10b disparity errors for a given channel, to determine and validate the incoming serial
data rate. The channel synchronization state machine is implemented as specified in IEEE802.3-2002
Clause 36, Figure 36-9, Page 62. The channel synchronization state machine flowchart is shown in
Figure 2-14 Channel Synchronization Flowchart. The 8b/10b decoder is used in tandem with the channel
synchronization state machine to determine if rate sense is successful at a particular device setting. Note
that the 8b/10b decoder is used for the ARS function even if 8b/10b encoding/decoding is disabled for the
datapath of the channel. Parallel output data is always output in the pin/software selected format (i.e.,
unencoded or 8b/10b encoded or byte aligned), and is not a function of whether ARS is enabled. Also
note that the RX SERDES CDR lock indication (AGCLOCK) qualifies channel synchronization.
When an ARS enabled channel is found to be in the channel synchronization state, the following rate
settings (RATE_TX[1:0] register bits 1.7:6, RATE_RX[1:0] register bits 1.5:4, PLL_MULT[3:0] register bits
1.3:0) are available to be read through the MDIO interface, as indicated by the per channel ARS Locked
register bit (ARS_LOCKED register bit 5.10) being asserted high. If the ARS function is not currently
locked onto the incoming serial data, the ARS locked register bit (ARS_LOCKED register bit 5.10) will
read deasserted, and the rate settings are not valid (although they are always readable). It is also possible
through MDIO configuration to make the inverse of ARS_LOCKED indication visible on the LOSA/B
outputs per channel, and in this mode can be used as a software interrupt notification. After a successful
rate determination is made, the ARS function will continue to monitor channel synchronization status. If
channel synchronization is lost, the ARS state machine will begin looping through SERDES settings
(reattempting with the last working setting one time rather than with the next different setting) until either
ARS is disabled or channel synchronization is achieved. The ARS state machine will stay in a particular
setting (expected serial rate) attempting to achieve rate determination for the number of reference clock
cycles programmed in ARS_INTERVAL[20:0] (per channel register bits 11.4:0 / 12.15:0), which indicates a
duration of time defined as the number of reference clock periods times 1024. This register is sized such
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