M16C1N Datasheet, PDF (93/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
12. Timers
Conditions: A period from one rising edge to the next rising edge of measurement pulse is measured. (R0EDG=0)
Timer X=0F16
fPX
"1"
Count start flag
"0"
Measurement pulse "1"
(CNTR0 pin input) _"0"
Timer X contents
Set to "1" by software (Note 7)
Count start
Timer X
reloads
Hold
Timer X
reloads
0F16 0E16 0D16 0F16 0E16 0D16 0C16 0B16 0A16 0916 0F16 0E16
Timer X
reloads
0116 0016 0F16 0E16
Contents of read
purpose buffer
(Note 1)
Effectual edge _"1"
reception flag _"0"
Timer X "1"
underflow flag _"0"
XX16
(Note 2)
0B16 0A16
0916
0D16
0116 0016 0F16 0E16
Timer X
Dummy read (Note 3)
(Note 2)
Timer X
Read by software
(Note 3)
Cleared to "0" by software (Note 4)
(Note 6)
Cleared to "0" by software (Note 5)
Timer X interrupt "1"
request bit _"0"
CNTR0 interrupt ^"1"
request bit _"0"
Cleared to "0" when interrupt request is accepted, or cleared by software
Cleared to "0" when interrupt request is accepted, or cleared by software
Note 1: If timer X is read out in pulse period measurement mode, the contents of the read purpose buffer can be read.
Note 2: After an active edge of measurement pulse is input, effectual edge reception flag (TXEDG) is set to "1" when the prescaler
X underflows for the second time.
Note 3: The timer X should be read out before the next active edge is input after TXEDG is set to "1". If the timer X is not read
before the next active edge is input, the value in the read purpose buffer remains unchanged and therefore is not updated
on an active edge.
Note 4: When set to "0" by software, use a MOV instruction to write "0" to the bit 6 (TXEDG) in the timer X mode register (008B16).
At the same time, write "1" to the bit 7 (TXUND).
Note 5: When set to "0" by software, use a MOV instruction to write "0" to the bit 7 (TXUND) in the timer X more register (008B16).
At the same time, write "1" to the bit 6 (TXEDG).
Note 6: If the timer X underflow flag (TXUND) and TXEDG are both set to "1". In this case, the validity of TXUND should be judged
by the contents of the read purpose buffer.
Note 7: When setting the timer X count start flag to "1", the timer X interrupt request bit and the effectual edge reception flag may
become "1".
Thus, the timer X interrupt must be enabled after setting the timer X count flag to "1" and clearing the timer X interrupt
request bit and the effectual edge reception flag to "0" with inhibiting the timer X interrupt.
Figure 12.12 Operation example in pulse width measurement mode
Rev.1.00 Oct 20, 2004 page 81 of 222
REJ09B0007-0100Z