M16C1N Datasheet, PDF (188/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
19. Flash Memory Version
ROM code protect control address
b7 b6 b5 b4 b3 b2 b1 b0
1111
Symbol
ROMCP
Address
0FFFFF16
Value when shipped
FF16 (Note 1)
Bit symbol
Bit name
Function
RW
(b3-b0) ^{Reserved bit}
Set this bit to "1"
RW
ROMCR
ROM code protect reset bit
b5 b4
0 0 : Removes protect
RW
(Note 1, 2)
} ^{0 1 :}
1 0 : Enables ROMCP1 bit
11:
RW
ROMCP1 ROM code protect level
1 set bit (Note 1, 3, 4)
b7 b6
} ^{0 0 :}
0 1 : Protect enabled
RW
10:
1 1 : Protect disabled
RW
Note 1: Once any of these bits is cleared to "0", it cannot be set back to "1". If a memory block that contains the
ROMCP register is erased, the ROMCP register is set to ’FF16’.
Note 2: If the ROMCR bits are set to ’002’ when the ROMCR bits are other than ’002’ and the ROMCP1 bits are oth-
er than ’112’, ROM code protect level 1 is removed. However, because the ROMCR bits cannot be modified
during parallel I/O mode, they need to be modified in standard serial I/O or other modes.
Note 3: If the ROMCR bits are set to other than ’002’ and the ROMCP1 bits are set to other than ’112’ (ROM code
protect enabled), the flash memory is disabled against reading and rewriting in parallel I/O mode.
Note 4: The ROMCP1 bits are effective when the ROMCR bits are ’012’, ’102’, or ’112’.
Figure 19.2 ROMCP register
Address
0FFFDC16 to 0FFFDF16 ID1 Undefined instruction vector
0FFFE016 to 0FFFE316 ID2 Overflow vector
0FFFE416 to 0FFFE716
BRK instruction vector
0FFFE816 to 0FFFEB16 ID3 Address match vector
0FFFEC16 to 0FFFEF16 ID4 Single step vector
0FFFF016 to 0FFFF316 ID5 Watchdog timer vector
0FFFF416 to 0FFFF716 ID6 DBC vector
0FFFF816 to 0FFFFB16 ID7 UART0 receive vector
0FFFFC16 to 0FFFFF16
Reset vector
Figure 19.3 ID code store addresses
4 bytes
Rev.1.00 Oct 20, 2004 page 176 of 222
REJ09B0007-0100Z