M16C1N Datasheet, PDF (209/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
19. Flash Memory Version
Table 19.7 Pin functions (Flash memory standard serial I/O mode)
Pin
Name
I/O
Description
VCC, VSS
Power input
I Apply the voltage guaranteed for program and erase to Vcc pin and 0 V to
Vss pin.
IVCC
CNVSS
RESET
IVCC input
CNVSS input
Reset input
I Connect a capacitor (0.1µF) to VSS pin.
I Connect to VCC pin
I Reset input pin. While RESET pin is "L" level, input a 20 cycle or longer clock
XIN
XOUT
VREF
P00 to P07
P10 to P13
P14
P15
P16
P17
Clock input
Clock output
Reference voltage input
Input port P0
Input port P1
TXD output
RXD input
SCLK input
BUSY output
to XIN pin.
I Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins.
O To input an externally generated clock, input it to XIN pin and open XOUT pin.
I Enter the reference voltage for AD from this pin. Connect to VCC or VSS pin.
I Input "H" or "L" level signal or open.
I Input "H" or "L" level signal or open.
O Serial data output pin (Note 1)
I Serial data input pin
I Standard serial I/O mode 1: Serial clock input pin.
Standard serial I/O mode 2: Input "L" level signal.
O Standard serial I/O mode 1: BUSY signal output pin
Standard serial I/O mode 2: Monitors the boot program operation check signal
output pin.
P20, P21
Input port P2
I Input "H" or "L" level signal or open.
P30
SEL input
I SEL signal input pin. Input "L" level signal.
P31
CE input
I CE signal input pin. Input "H" level signal.
P32 to P37 Input port P3
I Input "H" or "L" level signal or open.
P40 to P47 Input port P4
I Input "H" or "L" level signal or open.
P50 to P52 Input port P5
I Input "H" or "L" level signal or open.
___________
Note 1: When using standard serial I/O mode 1, the TxD pin must be held high while the RESET pin is low.
Therefore, connect this pin to VCC via a resistor. Because this pin is directed for data output after
reset, adjust the pull-up resistance value in the system so that data transfers will not be affected.
Rev.1.00 Oct 20, 2004 page 197 of 222
REJ09B0007-0100Z