M16C1N Datasheet, PDF (125/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
13. Serial I/O
13.1 Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data.
Table 13.1 lists specifications of clock synchronous sperial I/O mode. Figure 13.6 shows the UARTi
transmit/receive mode register.
Table 13.1 Specifications of clock synchronous serial I/O mode
Item
Transfer data format
Transfer clock
Transmission start
condition
Reception start
conditio
Interrupt request
generation timing
Error detection
Select function
Specification
• Transfer data length: 8 bits
• When internal clock is selected (bit 3 at address 00A016,00A816 = "0"): fi/ 2(n+1) (Note 1)
fi = f1, f8, f32, fc
• When external clock is selected (bit 3 at address 00A016,00A816 = "1"): Input from CLKi pin
• To start transmission, the following requirements must be met:
_ _{Transmit enable bit (bit 0 at address 00A516,00AD16) = "1"}
_ _{Transmit buffer empty flag (bit 1 at addresses 00A516,00AD16) = "0"}
• Furthermore, if external clock is selected, the following requirements must also be met:
_ _{CLKi polarity select bit (bit 6 at address 00A416,00AC16) = "0": CLKi input level = "H"}
_ _{CLKi polarity select bit (bit 6 at address 00A416,00AC16) = "1": CLKi input level = "L"}
• To start reception, the following requirements must be met:
_ _{Receive enable bit (bit 2 at address 00A516,00AD16) = "1"}
_ _{Transmit enable bit (bit 0 at address 00A516,00AD16) = "1"}
_ _{Transmit buffer empty flag (bit 1 at address 00A516,00AD16) = "0"}
• Furthermore, if external clock is selected, the following requirements must also be met:
_ _{CLKi polarity select bit (bit 6 at address 00A416,00AC16) = "0": CLKi input level = "H"}
_ _{CLKi polarity select bit (bit 6 at address 00A416,00AC16) = "1": CLKi input level = "L"}
• When transmitting
_ _{Transmit interrupt cause select bit (bit 0 and bit 1 at address 00B016) = "0": Inter-}
rupts requested when data transfer from UARTi transfer buffer register to UARTi
transmit register is completed
_ _{Transmit interrupt cause select bit (bit 0 and bit 1 at address 00B016) = "1": Inter-}
rupts requested when data transmission from UARTi transfer register is completed
• When receiving
_ _{Interrupts requested when data transfer from UARTi receive register to UARTi re-}
ceive buffer register is completed
• Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading
UARTi receive buffer register and received the 7th bit of the next data
• CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the transfer
clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection
UART1 transfer clock can be chosen by software to be output from one of the two pins set
• RxD1 input pin selection
UART1 RxD1 can be chosen by software to be input to one of the two pins set
Note 1: "n" denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: If an overrun error occurs, the UARTi receive buffer will be indeterminate. Note also that the UARTi
receive interrupt request bit does not change.
Rev.1.00 Oct 20, 2004 page 113 of 222
REJ09B0007-0100Z