M16C1N Datasheet, PDF (89/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
12. Timers
12.2.3 Event Counter Mode
In this mode, the timer counts an external signal fed to CNTR0 pin. (See Table 12.5) Figure 12.8
shows Timer X mode register in event counter mode.
Table 12.5 Specifications of event counter mode
Item
Specification
Count source
Count operation
External signals fed to CNTR0 pin (Active edge is selected by software)
• Down count
• When the timer underflows, it reloads the reload register contents before continuing
Divide ratio
counting
1
(n+1) X (m+1)
n: Set value of Prescaler X, m: Set value of Timer X
Count start condition
Count start flag is set (=1)
Count stop condition
Count start flag is reset (=0)
Interrupt request generation timing • When Timer X underflows [Timer X interruption]
CNTR0 pin function
TXOUT pin function
Read from timer
• Rising (R0EDG=0) or falling (R0EDG=1) of CNTR0 input [CNTR0 interruption]
Count source input
Programmable I/O port
Count value can be read out by reading Timer X register.
Write to timer
Same applies to Prescaler X register.
When a value is written to Timer X register, it is written to both reload register and counter.
Select function
Same applies to Prescaler X register.
• CNTR0 polarity switching function
The active edge of count source can be selected to be the rising or the falling edge with
software.
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
00
10
Symbol
TXMR
Address
008B16
When reset
0016
Bit symbol
Bit name
Function
RW
TXMOD0 ^{Operation mode}
select bit 0, 1
b1 b0
1 0 : Event counter mode
RW
TXMOD1
(Note 1)
RW
R0EDG
CNTR0 polarity
0 : Counts at rising edge (Interrupt at rising edge)
switching bit (Note 1) 1 : Counts at falling edge (Interrupt at falling edge)
RW
TXS
Timer X count
0 : Stops counting
start flag
1 : Starts counting
RW
TXOCNT P30/TXOUT
0 : Set to "0" in event counter mode
RW
select bit
TXMOD2 Operation mode
select bit 2
0 : Set to "0" in event counter mode
RW
TXEDG
Effectual edge
reception flag
Invalid in event counter mode.
When write, set "0". When read, this contents RW
is indeterminate.
TXUND
Timer X under
flow flag
Invalid in event counter mode.
When write, set "0". When read, this contents RW
is indeterminate.
Note 1: This bit should rewrite with inhibiting the CNTR0 interrupt. When using the interrupt, the interrupt must be enabled
after clearing the CNTR0 interrupt request bit to "0" using a MOV instruction.
Figure 12.8 Timer X mode register in event counter mode
Rev.1.00 Oct 20, 2004 page 77 of 222
REJ09B0007-0100Z