M16C1N Datasheet, PDF (120/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
13. Serial I/O
13. Serial I/O
Serial I/O is configured as two channels: UART0 and UART1. UART0 and UART1 each have an exclusive
timer to generate a transfer clock, so they operate independently of each other.
Figure 13.1 shows the block diagram of UARTi (i=0,1). Figure 13.2 shows the block diagram of the transmit/
receive unit.
UART0 has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/
O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 00A016 and
00A816) determine whether UART0 is used as a clock synchronous serial I/O or as a UART. Although a few
functions are different, UART0 and UART1 have almost the same functions.
Figures 13.3 through 13.5 show the registers related to UARTi.
(UART0)
RxD0
UART reception
1/16
Clock source selection
f1
Bit rate generator ^{Clock synchronous type}
f8
Internal (Address 00A116)
f32
1 / (n0+1)
UART transmission
1/16
fc
External
Clock synchronous type
Reception
control circuit
Transmission
control circuit
Clock synchronous type
(when internal clock is selected)
1/2
CLK0
CLK
polarity
reversing
circuit
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is selected)
Receive
clock
Transmit
clock
Transmit/
receive
unit
TxD0
(UART1)
RxD1
Clock source selection
UART reception
1/16
f1
f8
Bit rate generator ^{Clock synchronous type}
Internal _{(Address 00A916)}
f32
1 / (n1+1)
UART transmission
1/16
fc
External
Clock synchronous type
Reception
control circuit
Transmission
control circuit
Clock synchronous type
(when internal clock is selected)
1/2
Receive
clock
Transmit
clock
Transmit/
receive
unit
CLK1
CLKS1
Clock synchronous type
(when internal clock is selected)
CLK
polarity
reversing
circuit
Clock output pin
select switch
Clock synchronous type
(when external clock is selected)
n0: Values set to UART0 bit rate generator (BRG0)
n1: Values set to UART1 bit rate generator (BRG1)
TxD1
Figure 13.1 Block diagram of UARTi (i= 0, 1)
Rev.1.00 Oct 20, 2004 page 108 of 222
REJ09B0007-0100Z