M16C1N Datasheet, PDF (61/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
10. Interrupt
10.1.4.2 Variable Vector Tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indi-
cate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the
address the INTB indicates becomes the area for the variable vector tables. One vector table
comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 10.2
lists the interrupts assigned to the variable vector tables and addresses of vector tables.
Table 10.2 Interrupt causes (variable interrupt vector addresses)
Software interrupt number ^{Vector table address (Note 1)}
Address (L) to address (H)
Interrupt source
Remarks
0
+0 to +3
BRK instruction
Cannot be masked by I flag
1
+4 to +7
2
+8 to +11
3
+12 to +15
4
+16 to +19
5
+20 to +23
CAN0 wake up
6
+24 to +27
CAN0 error
7
+28 to +31
8
+32 to +35
CAN0 successful reception
9
+36 to +39
CAN0 successful transmission
10
+40 to +43
11
+44 to +47
12
+48 to +51
13
+52 to +55
Key input
14
+56 to +59
A/D
15
+60 to +63
16
+64 to +67
17
+68 to +71
UART0 transmission
18
+72 to +75
UART0 reception
19
+76 to +79
UART1 transmission
20
+80 to +83
UART1 reception
21
+84 to +87
Timer 1
22
+88 to +91
Timer X
23
+92 to +95
Timer Y
24
+96 to +99
Timer Z
25
+100 to +103
CNTR0
26
+104 to +107
TCIN
27
+108 to +111
Timer C
28
+112 to +115
INT3
29
+116 to +119
INT0
30
+120 to +123
INT1
31
+124 to +127
INT2
32
+128 to +131
to
to
software interrupt
Cannot be masked by I flag
63
+252 to +255
Note 1: Address relative to address in interrupt table register (INTB).
Rev.1.00 Oct 20, 2004 page 49 of 222
REJ09B0007-0100Z