M16C1N Datasheet, PDF (68/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
10. Interrupt
10.1.5.7 Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values
shown in Table 10.6 is set in the IPL.
Table 10.6 Relationship between interrupts without interrupt priority levels and IPL
Interrupt sources without priority levels
Value set in the IPL
Watchdog timer
7
Reset
0
Other
Not changed
10.1.5.8 Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program
counter (PC) are saved in the stack area.
First, the processor saves the 4 high-order bits of the program counter, and 4 high-order bits and 8
low-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 low-order bits of
the program counter. Figure 10.6 shows the state of the stack as it was before the acceptance of
the interrupt request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address
Stack area
MSB
LSB
m-4
m-3
m-2
m-1
m
Content of previous stack
m + 1 Content of previous stack
[SP]
Stack pointer
value before
interrupt occurs
Address
Stack area
MSB
LSB
m-4
Program counter (PCL)
m-3
Program counter (PCM)
m-2
m-1
m
Flag register (FLGL)
Flag register Program
(FLGH) counter (PCH)
Content of previous stack
m + 1 Content of previous stack
[SP]
New stack
pointer value
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
Figure 10.6 State of stack before and after acceptance of interrupt request
Rev.1.00 Oct 20, 2004 page 56 of 222
REJ09B0007-0100Z