M16C1N Datasheet, PDF (64/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
10. Interrupt
10.1.5.1 Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting
this flag to "1" enables all maskable interrupts; setting it to "0" disables all maskable interrupts.
This flag is set to "0" after reset.
10.1.5.2 Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt
is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hard-
ware. The interrupt request bit can also be set to "0" by software (Do not set this bit to "1").
10.1.5.3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the compo-
nent bits of the interrupt control register. When an interrupt request occurs, the interrupt priority
level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt
is higher than the IPL. Therefore, setting the interrupt priority level to "0" disables the interrupt.
Table 10.3 lists the settings of interrupt priority levels and Table 10.4 lists the interrupt levels en-
abled, according to the consist of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL
are independent, and they are not affected by one another.
Table 10.3 Settings of interrupt priority levels
Interrupt priority
level select bit
Interrupt priority
level
b2 b1 b0
000
001
Level 0
(interrupt disabled)
Level 1
010
Level 2
0 11
Level 3
100
Level 4
101
Level 5
11 0
Level 6
111
Level 7
Priority
order
Low
High
Table 10.4 Interrupt levels enabled according
to the contents of the IPL
IPL
Enabled interrupt priority levels
IPL2 IPL1IPL0
0 0 0 Interrupt levels 1 and above are enabled
0 0 1 Interrupt levels 2 and above are enabled
0 1 0 Interrupt levels 3 and above are enabled
0 1 1 Interrupt levels 4 and above are enabled
1 0 0 Interrupt levels 5 and above are enabled
1 0 1 Interrupt levels 6 and above are enabled
1 1 0 ^{Interrupt levels 7 and above are enabled}
1 1 1 ^{All maskable interrupts are disabled}
Rev.1.00 Oct 20, 2004 page 52 of 222
REJ09B0007-0100Z