M16C1N Datasheet, PDF (226/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
20. Precautionary Notes in Using the Device
20.6 CAN Module
20.6.1 Reading C0STR Register
The CAN module on the M16C/1N group updates the status of the C0STR register in a certain
period. When the CPU and the CAN module access to the C0STR register at the same time, the
CPU has the access priority; the access from the CAN module is disabled. Consequently, when
the updating period of the CAN module matches the access period from the CPU, the status of the
CAN module cannot be updated. (See Figure 20.2)
Accordingly, be careful about the following points so that the access period from the CPU should
not match the updating period of the CAN module:
1. There should be a wait time of 3fCAN or longer (see Table 20.1) before the CPU reads the C0STR
register. (See Figure 20.3)
2. When the CPU polls the C0STR register, the polling period must be 3fCAN or longer. (See Figure
20.4)
Table 20.1 CAN Module Status Updating Period
3fCAN period = 3 X XIN (Original oscillation period) X Division value of the CAN clock (CCLK)
(Example 1) Condition XIN 16MHz CCLK: Divided by 1
3fCAN period = 3 X 62.5 ns X 1= 187.5 ns
(Example 2) Condition XIN 16MHz CCLK: Divided by 2
3fCAN period = 3 X 62.5 ns X 2= 375 ns
(Example 3) Condition XIN 16MHz CCLK: Divided by 4
3fCAN period = 3 X 62.5 ns X 4= 750 ns
(Example 4) Condition XIN 16MHz CCLK: Divided by 8
3fCAN period = 3 X 62.5 ns X 8= 1.5 µs
(Example 5) Condition XIN 16MHz CCLK: Divided by 16 3fCAN period = 3 X 62.5 ns X 16= 3 µs
Rev.1.00 Oct 20, 2004 page 214 of 222
REJ090007-0100Z