M16C1N Datasheet, PDF (69/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
10. Interrupt
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer (Note 1), at the time of acceptance of an interrupt request, is even or
odd. If the content of the stack pointer (Note 1) is even, the content of the flag register (FLG) and
the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are
saved in two steps, 8 bits at a time. Figure 10.7 shows the operation of the saving registers.
Note 1: This is the stack pointer indicated by the U flag.
(1) Stack pointer (SP) contains even number
Address
Stack area
Sequence in which order
registers are saved
[SP] - 5 (Odd)
[SP] - 4 (Even)
Program counter (PCL)
[SP] - 3 (Odd)
Program counter (PCM)
[SP] - 2 (Even)
[SP] - 1 (Odd)
[SP] (Even)
Flag register (FLGL)
Flag register Program
(FLGH) counter (PCH)
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
Finished saving registers
in two operations.
(2) Stack pointer (SP) contains odd number
Address
Stack area
Sequence in which order
registers are saved
[SP] - 5 (Even)
[SP] - 4 (Odd)
Program counter (PCL)
[SP] - 3 (Even)
Program counter (PCM)
[SP] - 2 (Odd)
[SP] - 1 (Even)
[SP] (Odd)
Flag register (FLG
Flag register Program
(FLGH) counter (PCH)
(3)
(4) _{Saved simultaneously,}
all 8 bits
(1)
(2)
Finished saving registers
in four operations.
Note 1: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is
acknowledged. After registers are saved, the SP content is [SP] minus 4.
Figure 10.7 Operation of saving registers
Rev.1.00 Oct 20, 2004 page 57 of 222
REJ09B0007-0100Z