M16C1N Datasheet, PDF (80/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
11. Watchdog Timer
11. Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system. The watchdog timer is a 15-bit counter
which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt
or reset is generated when an underflow occurs in the watchdog timer. A watchdog timer interrupt or reset
is selected by bit 2 of the processor mode register 1. When XIN is selected for the BCLK, bit 7 of the
watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128).
When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog
timer control register (address 000F16).
When XIN is selected in BCLK
Prescaler division ratio (16 or 128) x watchdog timer count (32768)
Watchdog timer cycle =
BCLK
When XCIN is selected in BCLK
Watchdog timer cycle =
Prescaler division ratio (2) x watchdog timer count (32768)
BCLK
For example, when BCLK is 10MHz and the prescaler division ratio is set to 16, the watchdog timer cycle is
approximately 52.4 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16).
Figure 11.1 shows the block diagram of the watchdog timer. Figure 11.2 shows the watchdog timer-related
registers.
BCLK
Write to the watchdog timer
start register
(address 000E16)
RESET
Prescaler
1/16
"CM07 = 0"
"WDC7 = 0"
1/128
"CM07 = 0"
"WDC7 = 1"
"CM07 = 1"
1/2
Watchdog timer
"PM12=0"
"PM12=1"
Watchdog timer
interrupt request
Reset (Note 1)
Set to
"7FFF16"
Note 1: This bit is set to "1" once, can not be clear to "0" by software.
Figure 11.1 Block diagram of watchdog timer
Rev.1.00 Oct 20, 2004 page 68 of 222
REJ09B0007-0100Z