M16C1N Datasheet, PDF (132/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
13. Serial I/O
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Tc
Transfer clock
Transmit enable ^"1"
bit (TE)
"0"
Transmit buffer ^"1"
empty flag (TI) _"0"
TxDi
Transmit register _"1"
empty flag
(TXEPT)
"0"
Transmit interrupt ^"1"
request bit (IR) _"0"
Data is set in UARTi transmit buffer register.
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
Parity Stop
bit
bit
Stopped pulsing because transmit enable bit = "0"
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
Parity is enabled.
One stop bit.
Transmit interrupt cause select bit = 1.
Cleared to "0" when interrupt request is accepted, or cleared by software
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32, fc)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
Transmit enable ^"1"
bit (TE)
"0"
Transmit buffer ^"1"
empty flag (TI) _"0"
TxDi
Transmit register "1"
empty flag
(TXEPT)
"0"
Transmit interrupt ^"1"
request bit (IR) _"0"
Data is set in UARTi transmit buffer register
Start
bit
Transferred from UARTi transmit buffer register to UARTi transmit register
Stop Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1
Cleared to "0" when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
Parity is disabled.
Two stop bits.
Transmit interrupt cause select bit = 0.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32, fc)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
Figure 13.12 Typical transmit timings in UART mode
Rev.1.00 Oct 20, 2004 page 120 of 222
REJ09B0007-0100Z