M16C1N Datasheet, PDF (88/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
12. Timers
12.2.2 Pulse Output Mode
In this mode, the timer counts an internally generated count source, and outputs from the CNTR0 pin
a pulse whose polarity is inverted each time the timer underflows.
(See Table 12.4) Figure 12.7 shows Timer X mode register in pulse output mode.
Table 12.4 Specifications of pulse output mode
Item
Specification
Count source
f1, f8, f32, fC32
Count operation
• Down count
Divide ratio
• When the timer underflows, it reloads the reload register contents before continuing counting
1
(n+1) X (m+1)
n: Set value of Prescaler X, m: Set value of Timer X
Count start condition
Count start flag is set (=1)
Count stop condition
Count start flag is reset (=0)
Interrupt request generation timing • When Timer X underflows [Timer X interruption]
• Rising (R0EDG=0) or falling (R0EDG=1) of CNTR0 output [CNTR0 interruption]
CNTR0 pin function
Pulse output
TXOUT pin function
Programmable I/O port or pulse output (Inverted waveform of the pulse output from the
CNTR0 pin)
Read from timer
Count value can be read out by reading Timer X register.
Same applies to Prescaler X register.
Write to timer
When a value is written to Timer X register, it is written to both reload register and counter.
Same applies to Prescaler X register.
Select function
• Pulse output function
Each time the timer underflows, the TXOUT pin’s polarity is reversed
• CNTR0 polarity switching function
The polarity level at starting of pulse output can be selected to be "High" or "Low" with software.
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
01
Symbol
TXMR
Address
008B16
When reset
0016
Bit symbol
Bit name
Function
RW
TXMOD0 ^{Operation mode}
select bit 0, 1
b1 b0
0 1 : Pulse output mode (Note 1)
RW
TXMOD1
(Note 2)
RW
R0EDG
CNTR0 polarity
0 : Output starts at "H" (Interrupt at rising edge)
switching bit (Note 2) 1 : Output starts at "L" (Interrupt at falling edge)
RW
TXS
Timer X count
start flag
0 : Stops counting
1 : Starts counting
RW
TXOCNT
P30/TXOUT
select bit
0 : Port P30
1 : TXOUT output (Note 3)
RW
TXMOD2 Operation mode
0 : Set to "0" in pulse output mode
RW
select bit 2
TXEDG
Effectual edge
reception flag
Invalid in pulse output mode.
When write, set "0". When read, this contents
RW
is indeterminate.
TXUND
Timer X under
flow flag
Invalid in pulse output mode.
When write, set "0". When read, this contents RW
is indeterminate.
Note 1: In the pulse output mode, the direction register of port P17 must be set to input.
Note 2: This bit should rewrite with inhibiting the CNTR0 interrupt. To use this interrupt, enable an interrupt after the
CNTR0 interrupt request bit is cleared with the MOV instruction.
Note 3: Output is set regardless of the setting of the direction register of port P30.
Figure 12.7 Timer X mode register in pulse output mode
Rev.1.00 Oct 20, 2004 page 76 of 222
REJ09B0007-0100Z