M16C1N Datasheet, PDF (136/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
14. A/D Converter
A/D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
ADCON0
Address
00D616
When reset
00000XXX2
Bit symbol
Bit name
Function
RW
CH0
CH1
CH2
Analog input pin select bit ^{b2 b1 b0}
0 0 0 : AN0 is selected
RW
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
RW
1 0 0 : AN4, AN8 are selected
1 0 1 : AN5, AN9 are selected
1 1 0 : AN6, AN10 are selected
RW
1 1 1 : AN7, AN11 are selected (Note 2, 3)
MD
A/D operation mode
0 : One-shot mode
select bit 0
1 : Repeat mode (Note 2)
RW
ADGSEL0 A/D input group select bit 0 : Port P0 group is selected
1 : Port P1 group is selected
RW
Reserved bit
Set to "0"
RW
ADST
A/D conversion start flag
0 : A/D conversion disabled
1 : A/D conversion started
RW
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
RW
Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate.
Note 2: When changing A/D operation mode, set analog input pin again.
Note 3: AN4 to AN7 and AN8 to AN11 are selected by the A/D input group select bit.
A/D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol
ADCON1
Address
00D716
When reset
0016
Bit symbol
Bit name
Function
RW
Reserved bit
Set to "0"
RW
BITS
8/10-bit mode select bit 0 : 8-bit mode
(Note 2) 1 : 10-bit mode
RW
CKS1 Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
(Note 3) 1 : fAD is selected
RW
VCUT VREF connect bit
0 : VREF not connected
1 : VREF connected
RW
OPA0
OPA1
External op-amp
connection mode bit
b7 b6
0 0 : ANEX0 and ANEX1 are not used RW
0 1 : ANEX0 input is A/D converted
1 0 : ANEX1 input is A/D converted
1 1 : External op-amp connection mode
RW
Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate.
Note 2: In repeat mode, only 8-bit mode can be used.
Note 3: When f(XIN) is over 10 MHz, the flAD frequency must be under 10 MHz by dividing.
Figure 14.2 A/D converter-related registers (1)
Rev.1.00 Oct 20, 2004 page 124 of 222
REJ09B0007-0100Z