M16C1N Datasheet, PDF (38/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
6. Clock Generation Circuit
Oscillation stop detection register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0 000
Symbol
CM2
Address
000C16
When reset
000001002
Bit symbol
Bit name
CM20 Oscillation stop
detection bit
Function
RW
0 : The function is invalid
1 : The function is valid (Note 2)
RW
CM21
Oscillation stop detection 0 : Disabled
interrupt enable bit
1 : Enabled (Note 3)
RW
CM22 Main clock switch bit
0 : Select XIN clock
1 : Select on-chip oscillator (Note 4)
RW
CM23
Clock monitor bit (Note 5) 0 : XIN oscillating normally
1 : XIN stopping abnormally
RO
Reserved bit
Set to "0"
RW
Note 1: In case of writing to this register, set bit 0 of the protect register (address 000A16) to "1".
Note 2: Set to "0" before stopping the oscillation of the main clock (XIN-XOUT).
(stop mode, low power dissipation mode, on-chip oscillation mode)
An oscillation stop is detected if the oscillation of the main clock (XIN-XOUT) is stopped when the following
two conditions are satisfied: (1) the oscillation stop detection function is valid and (2) CM21=1.
Note 3: Valid when CM20=1.
Note 4: CM22 bit switches to "1" automatically if an oscillation stop is detected when both CM20 bit and CM 21 bit
are "1". CM22 bit cannot be cleared when CM23=1.
Note 5: This bit is valid when both CM20 bit is "1". Use this bit for the purpose of confirming XIN operation for
oscillation stop detection interrupt execution.
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
008F16
When reset
0XXXXXXX2
Bit symbol
Bit name
Function
RW
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.
CPSR
Clock prescaler reset flag 0 : No effect
1 : Prescaler is reset
RW
(When read, the value is "0")
Figure 6.3 Oscillation stop detection register and clock prescaler reset flag
XCIN
Clock prescaler
1/32
Clock prescaler reset flag (bit 7
at address 008F16) set to "1"
Reset
Figure 6.4 fC32 block diagram
fC32
Rev.1.00 Oct 20, 2004 page 26 of 222
REJ09B0007-0100Z