M16C1N Datasheet, PDF (71/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
10. Interrupt
Priority level of each interrupt
INT1
INT3
TCIN
Timer Z
Timer X
Level 0 (initial value)
High
CAN0 error
INT2
INT0
Timer C
CNTR0
Timer Y
CAN0 wake up
UART1 reception
UART0 reception
Priority of peripheral I/O
interrupts
(if priority levels are same)
A/D conversion
CAN0 successful reception
Timer 1
UART1 transmission
UART0 transmission
Key input
CAN0 successful transmission
Processor interrupt priority level (IPL)
Low
Interrupt enable flag (I flag)
Address match
Oscillation stop detection/Watchdog timer
DBC (Note 1)
UART0 reception (Note 1)
Reset
UART0 receive hardware
interrupt enable bit
Note 1: Interrupts used for debugging purposes only.
Interrupt request level
judgment output signal
Interrupt
request
accepted
Figure 10.9 Interrupt resolution circuit
Rev.1.00 Oct 20, 2004 page 59 of 222
REJ09B0007-0100Z