M16C1N Datasheet, PDF (77/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
10. Interrupt
10.6 Address Match Interrupt
An address match interrupt is generated immediately before the instruction at the address indicated by
the address match interrupt register is executed. Two address match interrupts can be set, each of which
can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not
affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the
program counter (PC) for an address match interrupt varies depending on the instruction being executed.
Figure 10.16 shows the address match interrupt-related registers.
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Address
000916
When reset
XXXXXX002
Bit symbol
Bit name
Function
RW
AIER0
Address match interrupt 0 0 : Interrupt disabled
enable bit 1 : Interrupt enabled
RW
AIER1
Address match interrupt 1 0 : Interrupt disabled
enable bit 1 : Interrupt enabled
RW
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read,
turns out to be indeterminate.
Address match interrupt register i (i = 0, 1)
(b23)
(b19) (b16)(b15)
(b8)
b7
b3
b0 b7
b0 b7
b0
Symbol
Address
RMAD0
001216 to 001016
RMAD1
001616 to 001416
When reset
XXXX00002, 000000002, 000000002
Function
Values that can be set RW
Address setting register for address match interrupt 0000016 to FFFFF16 RW
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read,
turns out to be indeterminate.
Figure 10.16 Address match interrupt-related registers
Rev.1.00 Oct 20, 2004 page 65 of 222
REJ09B0007-0100Z