M16C1N Datasheet, PDF (62/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
10. Interrupt
10.1.5 Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level
select bit, and processor interrupt priority level (IPL). Whether an interrupt request is present or absent
is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selec-
tion bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I
flag) and the IPL are located in the flag register (FLG).
Figure 10.3 shows the interrupt control registers.
Rev.1.00 Oct 20, 2004 page 50 of 222
REJ09B0007-0100Z