M16C1N Datasheet, PDF (51/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
6. Clock Generation Circuit
Figure 6.12 shows the flow of interrupt cause determination of oscillation stop detection or watchdog
timer interrupt.
Oscillation stop detection interrupt
or watchdog timer interrupt
is generated
Read oscillation stop
detection register
NO
CM23=1?
YES
CM21=1 and
NO
CM22=1?
YES
Clear CM21 bit (Note 1)
Jump to the execution
program for oscillation stop
detection interrupt
Jump to the execution
program for watchdog timer
interrupt
Note 1: Disables multiple interrupts of oscillation stop detection and let watchdog
timer take priority.
Figure 6.12 Flow of interrupt cause determination
Rev.1.00 Oct 20, 2004 page 39 of 222
REJ09B0007-0100Z